Abstract: A method includes receiving instructions to render an image comprising content defined by a two-dimensional (2D) primitive; determining a portion of the 2D primitive covering a tile of multiple tiles of the image; generating an edge definition to represent an edge of the portion of the 2D primitive; and for each row of pixels within at least a portion of the tile containing the portion of the 2D primitive: identifying, based on the edge definition, a left-most pixel and right-most pixel in the row that intersect the edge; identifying, based on the left-most pixel and the right-most pixel, a set of first pixels in the row intersecting the edge; determining, for each first pixel in the set, a coverage weight indicating a proportion of the first pixel covered by the 2D primitive; and determining color information for the set of first pixels based on the associated coverage weights.

Abstract: Provided are a method and an apparatus for debugging, and a system on chip. The method for debugging includes: a component to be debugged receives a debugging instruction from a controller, and the component to be debugged performs debugging operation according to the debugging instruction and configuration of a state machine inside the component to be debugged. Then an SW level debugging operation of component on system on chip can be achieved, which improves the debugging efficiency of these components with large amounts of data flow on system on chip.

Abstract: Provided are an acceleration method, an apparatus and a system on chip. The acceleration method includes: the accelerator receives N-th parameter information of an N-th layer from a controller, wherein M layer of the deep neural network correspond to M application specific integrated circuit in the accelerator, wherein M and N are positive integer, M?2, 1?N?M, executes computation of the N-th layer according to the N-th parameter information, and transmits N-th computation result information of the N-th layer indicates that the computation of the N-th layer is completed, to the controller, wherein the computation result information comprises computation result of the N-th layer. Then a complete flexibility for ASIC implementations of hardware accelerator can be achieved, and any kind of DNN based algorithms can be supported, which improves the universality of the accelerator.

Abstract: Provided are a method and an apparatus for debugging, and a system on chip. The method for debugging includes: a component to be debugged receives a debugging instruction from a controller, and the component to be debugged performs debugging operation according to the debugging instruction and configuration of a state machine inside the component to be debugged. Then an SW level debugging operation of component on system on chip can be achieved, which improves the debugging efficiency of these components with large amounts of data flow on system on chip.