Abstract: In some aspects, the present disclosure provides a method for scaling a core processor clock to reduce power consumption. The method includes retrieving, by an advanced peripheral bus (APB) driver, a first one or more values from one or more registers of a core processor, the first one or more values corresponding to a set of instructions of the core processor. The method may also include determining, by an IPC calculator, a first expected instruction per cycle (IPC) for executing the set of instructions based on the first one or more values. The method may also include comparing, by the IPC calculator, a threshold IPC to the first expected IPC to determine whether an equality condition is met, wherein the threshold IPC is stored in a first register of the IPC calculator.

Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.

Abstract: Systems and methods for memory power management may receive a wake up event in retention mode that may be used to control three memory sequencers that wake up respective groups of memory sequencers.

Abstract: Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

Abstract: Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides multiple processor cores, each residing within its own processor core power domain. Each processor core is provided with a private cache residing within its own private cache power domain, configured to be power-controlled independently of the corresponding processor core power domain. When a first processor core is placed in a power-collapsed state, a snoop controller corresponding to the private cache of the first processor core maintains power to the private cache power domain of the private cache, allowing the private cache to remain online. The snoop controller also enables allocation and snooping of the private cache by a second processor core while the first processor core remains in the power-collapsed state. In this manner, each private cache may be used for data-caching operations while its corresponding processor core is power-collapsed.

Abstract: A system is disclosed. The system comprises a set-associative memory cache comprising a plurality of ways, a plurality of way power controllers (WPCs), each WPC being respectively associated with a respective way of the plurality of ways, and a cache controller. The cache controller is configured to provide a way activation signal to each of the plurality of WPCs, wherein the way activation signal includes either a power relay signal or a power mask signal. Each of the plurality of WPCs is configured to receive a power management signal, relay the power management signal to the respective way in response to a determination that the way activation signal is a power relay signal, and mask the power management signal to the respective way in response to a determination that the way activation signal is a power mask signal.

Abstract: Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

Abstract: Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whether a transaction request is of a first category rather than a second category. First-category bus transaction requests are stored in a buffer. Transaction request traffic between the bus interconnect system and one or more client components may also be monitored. It may be determined whether an aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than a threshold. If the aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than the threshold, buffered bus transaction requests may be transferred to the bus interconnect system.

Abstract: Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides multiple processor cores, each residing within its own processor core power domain. Each processor core is provided with a private cache residing within its own private cache power domain, configured to be power-controlled independently of the corresponding processor core power domain. When a first processor core is placed in a power-collapsed state, a snoop controller corresponding to the private cache of the first processor core maintains power to the private cache power domain of the private cache, allowing the private cache to remain online. The snoop controller also enables allocation and snooping of the private cache by a second processor core while the first processor core remains in the power-collapsed state. In this manner, each private cache may be used for data-caching operations while its corresponding processor core is power-collapsed.