Abstract: A package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.

Abstract: Embodiments described herein relate to lithographically defined vertical interconnect accesses (litho-vias) for a bridge die first level interconnect (FLI) and techniques of fabricating such litho-vias. In one example, a package substrate comprises a bridge die embedded in the package substrate; a first contact pad outside a perimeter of the bridge die; a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via; a third pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via. The first contact pad has a surface finish disposed thereon. A first protruded interconnect structure is positioned on the first via and a second protruded interconnect structure is positioned on the second via. Each of the first and second vias have sidewalls that are substantially vertical.

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.

Abstract: This document discusses, among other things, a stress-tolerant composite microelectronic material comprising a composite nanofiller including a nanofiller core material having a modulus greater than a core material composed of silicon dioxide (SiO2) alone, and an outer layer of oxidized nanofiller core material surrounding the nanofiller core material.