Patents by Inventor SIDDHARTH KATARE

SIDDHARTH KATARE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180004281
    Abstract: A reception interface circuit includes a reception buffer, a voltage generation circuit and a reception limiting circuit. The reception buffer receives an input signal through an input-output node to generate a buffer signal. The voltage generation circuit generates at least one control voltage based on a reflection characteristic at the input-output node. The reception limiting circuit is connected to the input-output node and limits at least one of a maximum voltage level and a minimum voltage level of the input signal based on the at least one control voltage. Power consumption may be reduced by limiting at least one of the maximum voltage level and the minimum voltage level of the input signal based on the reception characteristic at the input-output node using the reception limiting circuit, and an increased eye margin may be provided in comparison with a conventional termination circuit having the same power consumption.
    Type: Application
    Filed: February 7, 2017
    Publication date: January 4, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woon KANG, Siddharth KATARE, Jeong-Don IHM
  • Publication number: 20170316833
    Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.
    Type: Application
    Filed: March 8, 2017
    Publication date: November 2, 2017
    Inventors: Jeong-don IHM, Siddharth KATARE, Hyun-jin KIM
  • Publication number: 20170047925
    Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.
    Type: Application
    Filed: April 28, 2016
    Publication date: February 16, 2017
    Inventors: SIDDHARTH KATARE, JEONG-DON IHM