Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

Abstract: A regulator circuit includes a power transistor, a current mirror, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to an external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current mirror provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.

Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.

Abstract: A reception interface circuit includes a reception buffer, a voltage generation circuit and a reception limiting circuit. The reception buffer receives an input signal through an input-output node to generate a buffer signal. The voltage generation circuit generates at least one control voltage based on a reflection characteristic at the input-output node. The reception limiting circuit is connected to the input-output node and limits at least one of a maximum voltage level and a minimum voltage level of the input signal based on the at least one control voltage. Power consumption may be reduced by limiting at least one of the maximum voltage level and the minimum voltage level of the input signal based on the reception characteristic at the input-output node using the reception limiting circuit, and an increased eye margin may be provided in comparison with a conventional termination circuit having the same power consumption.

Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

Abstract: A regulator circuit includes a power transistor, a current minor, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current minor provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.

Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.