Patents by Inventor Siddharth Rajan

Siddharth Rajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200404095
    Abstract: Exemplary embodiments of the present disclosure are directed towards a system for monitoring telephony communications in real time, comprising: first user communication devices and second user communication devices are connected to a first provider communication device and a second provider communication device.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Inventors: Sarthak Singhal, Siddharth Ramesh, Govind Rajan M
  • Patent number: 10812651
    Abstract: Exemplary embodiments of the present disclosure are directed towards a system for monitoring telephony communications in real time, comprising: first user communication devices and second user communication devices are connected to a first provider communication device and a second provider communication device.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 20, 2020
    Assignee: EXOTEL TECHCOM PVT. LTD.
    Inventors: Sarthak Singhal, Siddharth Ramesh, Govind Rajan M
  • Publication number: 20200075809
    Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 ?m before reaching the inclined sidewall.
    Type: Application
    Filed: May 1, 2018
    Publication date: March 5, 2020
    Inventors: Siddharth RAJAN, Yuewei ZHANG, Zane JAMAL-EDDINE, Fatih AKYOL
  • Publication number: 20200006500
    Abstract: Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Siddharth Rajan, Zhanbo Xia, Caiyu Wang
  • Publication number: 20190320064
    Abstract: Exemplary embodiments of the present disclosure are directed towards a system for monitoring telephony communications in real time, comprising: first user communication devices and second user communication devices are connected to a first provider communication device and a second provider communication device.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Inventors: Sarthak Singhal, Siddharth Ramesh, Govind Rajan M
  • Publication number: 20180076354
    Abstract: An example ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include an n-doped contact region, an active region configured to emit UV light that is arranged between an n-doped region and a p-doped region, and a tunnel junction. The tunnel junction is arranged between the n-doped contact region and the p-doped region. In addition, the tunnel junction can include a heavily p-doped region, a degenerately n-doped region, and a semiconductor region arranged between the heavily p-doped region and the degenerately n-doped region. Each of the heavily p-doped region and the degenerately n-doped region has a gradually varied material energy bandgap to reduce respective depletion barriers within the heavily p-doped region and the degenerately n-doped region.
    Type: Application
    Filed: March 28, 2016
    Publication date: March 15, 2018
    Inventors: Siddharth RAJAN, Sriram KRISHNAMOORTHY, Yuewei ZHANG
  • Publication number: 20170033187
    Abstract: This disclosure relates to a novel approach towards enhancing the threshold voltage of an enhancement-mode field-effect-transistor (E-mode FET) using doped or polarization-graded buffer layers and utilizing drain-connected field plates to engineer peak fields. Enhancement-mode field effect transistors (E-mode FETs) with doped buffer layers replacing conventional undoped buffer layers could enable larger threshold voltages, owing to higher capacitance from the back. These FETs with larger threshold voltages, however, would experience large operational electric fields near the drain contact. Described herein are embodiments of an E-mode FET further comprised of doped buffer layer(s) in the structure of the HEMT to enable larger positive threshold voltages, with optional one or more drain field plates that modify the electric field profile in the channel of the device and improve device breakdown characteristics.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 2, 2017
    Inventors: Siddharth Rajan, Sanyam Bajaj
  • Patent number: 9478699
    Abstract: A nanowire comprises a polar semiconductor material that is compositionally graded along the nanowire from a first end to a second end to define a polarization doping profile along the nanowire from the first end to the second end. The polar semiconductor material may comprise a group IH-nitride semiconductor, such as an alloy of GaN and AlN, or an alloy of GaN and InN. Such nanowires may be formed by nucleating the first ends on a substrate, growing the nanowires by depositing polar semiconductor material on the nucleated first ends on a selected growth face, and compositionally grading the nanowires during growth to impart the polarization doping. The direction of the compositional grading may be reversed during the growing of the nanowires to reverse the type of the imparted polarization doping. In some embodiments, the reversing forms n/p or p/n junctions in the nanowires.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 25, 2016
    Assignee: THE OHIO STATE UNIVERSITY
    Inventors: Roberto C. Myers, Siddharth Rajan
  • Patent number: 8697506
    Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 15, 2014
    Assignee: General Electric Company
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Publication number: 20130207075
    Abstract: A nanowire comprises a polar semiconductor material that is compositionally graded along the nanowire from a first end to a second end to define a polarization doping profile along the nanowire from the first end to the second end. The polar semiconductor material may comprise a group IH-nitride semiconductor, such as an alloy of GaN and AlN, or an alloy of GaN and InN. Such nanowires may be formed by nucleating the first ends on a substrate, growing the nanowires by depositing polar semiconductor material on the nucleated first ends on a selected growth face, and compositionally grading the nanowires during growth to impart the polarization doping. The direction of the compositional grading may be reversed during the growing of the nanowires to reverse the type of the imparted polarization doping. In some embodiments, the reversing forms n/p or p/n junctions in the nanowires.
    Type: Application
    Filed: August 25, 2011
    Publication date: August 15, 2013
    Applicant: THE OHIO STATE UNIVERSITY
    Inventors: Roberto C. Myers, Siddharth Rajan
  • Publication number: 20120171824
    Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Patent number: 8159002
    Abstract: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: April 17, 2012
    Assignee: General Electric Company
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Patent number: 7948011
    Abstract: A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: May 24, 2011
    Assignee: The Regents of the University of California
    Inventors: Siddharth Rajan, Chang Soo Suh, James S. Speck, Umesh K. Mishra
  • Patent number: 7935985
    Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 3, 2011
    Assignee: The Regents of the University of Califonia
    Inventors: Umesh K. Mishra, Yi Pei, Siddharth Rajan, Man Hoi Wong
  • Publication number: 20100264461
    Abstract: A novel enhancement mode field effect transistor (FET), such as a High Electron Mobility Transistors (HEMT), has an N-polar surface uses polarization fields to reduce the electron population under the gate in the N-polar orientation, has improved dispersion suppression, and low gate leakage.
    Type: Application
    Filed: September 18, 2006
    Publication date: October 21, 2010
    Inventors: Siddharth Rajan, Chang Soo Suh, James S. Speck, Umesh K. Mishra
  • Publication number: 20090159929
    Abstract: A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
  • Publication number: 20090140293
    Abstract: A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Vinayak Tilak, Siddharth Rajan, Ho-Young Cha
  • Patent number: 7525130
    Abstract: Novel GaN/AlGaN metal-semiconductor field-effect transistor (MESFET) structures grown without any impurity doping in the channel. A high-mobility polarization-induced bulk channel charge is created by grading the channel region linearly from GaN to Al0.3Ga0.7N over a distance, e.g., 1000 ?. A polarization-doped field effect transistor (PolFET) was fabricated and tested under DC and RF conditions. A current density of 850 mA/mm and transconductance of 93 mS/mm was observed under DC conditions. Small-signal characterization of 0.7 ?m gate length devices had a cutoff frequency, f?=19 GHz, and a maximum oscillation of fmax=46 GHz. The PolFETs perform better than comparable MESFETs with impurity-doped channels, and are suitable for high microwave power applications. An important advantage of these devices over AlGaN/GaN HEMTs is that the transconductance vs. gate voltage profile can be tailored by compositional grading for better large-signal linearity.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: April 28, 2009
    Assignee: The Regents of the University of California
    Inventors: Umesh K. Mishra, Huili Xing, Debdeep Jena, Siddharth Rajan
  • Publication number: 20090085065
    Abstract: A method for fabricating III-N semiconductor devices on the N-face of layers comprising (a) growing a III-nitride semiconductor device structure in a Ga-polar direction on a substrate, (b) attaching a Ga face of the III-nitride semiconductor device structure to a host substrate, and (c) removing the substrate to expose the N-face surface of the III-nitride semiconductor device structure. An N-polar (000-1) oriented III-nitride semiconductor device is also disclosed, comprising one or more (000-1) oriented nitride layers, each having an N-face opposite a group III-face, wherein at least one N-face is an at least partially exposed N-face, and a host substrate attached to one of the group III-faces.
    Type: Application
    Filed: March 31, 2008
    Publication date: April 2, 2009
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Lee S. McCarthy, Chang Soo Suh, Siddharth Rajan
  • Publication number: 20080237640
    Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Umesh K. Mishra, Yi Pei, Siddharth Rajan, Man Hoi Wong