Abstract: Disclosed herein are etching methods, patterned substrates made using said methods, and methods of use of said patterned substrates. For example, described herein are methods comprising: oxidizing at least a portion of a surface of a substrate comprising a group III-V compound, thereby forming an oxidized layer at said portion of the surface; and etching the oxidized layer by exposing the oxidized layer to an etchant; wherein: the group III-V compound comprises one or more group III elements (e.g., Al, Ga, In, B, Sc, Y, or a combination thereof) and a group V element (e.g., N, As, or Sb); the etchant comprises at least one of the group III elements; and the etchant removes oxides by the etchant reacting with the oxide to form a suboxide, which desorbs from the surface.

Abstract: A method for using gallium beam flux in an ultra-low vacuum environment to etch Ga2O3 epilayer surfaces is provided. An Ga2O3 epilayer surface (105) is patterned by applying a SiO2 mask (107) that corresponds to a desired structure (810). The patterned surface is then placed in an ultra-low vacuum environment (130) and is heated to a very high temperature (820; 830). At the same time, a gallium flux is supplied to the patterned surface in the ultra-low vacuum environment (840). The gallium flux causes etching in the patterned surface that is not covered by the SiO2 mask. Using this method, sub-micron (˜100 nm) three-dimensional (3D) structures like fins, trenches, and nano-pillars can be fabricated with vertical sidewalls.

Abstract: Disclosed herein are semiconductor devices with a compositionally graded layer, and methods of making and use thereof.

Abstract: Methods are provided of selectively obtaining n-type and p-type regions from the same III-Nitride layer deposited on a substrate without using diffusion or ion-implantation techniques. The III-Nitride layer is co-doped simultaneously with n-type and p-type dopants, with p-type dopant concentration higher than n-type dopant to generate p-n junctions. The methods rely on obtaining activated p-type dopants only in selected regions to generate p-type layers, whereas the rest of the regions effectively behave as an n-type layer by having deactivated p-type dopant atoms.

Abstract: A hybrid Schottky diode is described herein where the forward characteristics are determined by the metal-semiconductor junction, and the reverse characteristics and breakdown are determined by the metal/dielectric/semiconductor junction. Experimental demonstration of such hybrid Schottky diodes shows significant improvement in the breakdown performance with average breakdown field up to 2.22 MV/cm with reduced turn on of 0.47 V and enable state-of-art power switching figure of merit for GaN lateral Schottky diodes.

Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 µm before reaching the inclined sidewall.

Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 ?m before reaching the inclined sidewall.

Abstract: A device is provided that comprises a first layer deposited onto a second layer. The second layer comprises a lightly doped n-type or p-type semiconductor drift layer, and the first layer comprises a high-k material with a dielectric constant that is at least two times higher than the value of the second layer. A metal Schottky contact is formed on the first layer and a metal ohmic contact is formed on the second layer. Under reverse bias, the dielectric constant discontinuity leads to a very low electric field in the second layer, while the electron barrier created by the first layer stays almost flat. Under forward bias, electrons flow through the first layer, into the metal ohmic contact. For small values of conduction band offset or valence band offset between the first layer and the second layer, the device is expected to support efficient electron or hole transport.

Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 ?m before reaching the inclined sidewall.

Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 ?m before reaching the inclined sidewall.

Abstract: A hybrid Schottky diode is described herein where the forward characteristics are determined by the metal-semiconductor junction, and the reverse characteristics and breakdown are determined by the metal/dielectric/semiconductor junction. Experimental demonstration of such hybrid Schottky diodes shows significant improvement in the breakdown performance with average breakdown field up to 2.22 MV/cm with reduced turn on of 0.47 V and enable state-of-art power switching figure of merit for GaN lateral Schottky diodes.

Abstract: Methods are provided of selectively obtaining n-type and p-type regions from the same III-Nitride layer deposited on a substrate without using diffusion or ion-implantation techniques. The III-Nitride layer is co-doped simultaneously with n-type and p-type dopants, with p-type dopant concentration higher than n-type dopant to generate p-n junctions. The methods rely on obtaining activated p-type dopants only in selected regions to generate p-type layers, whereas the rest of the regions effectively behave as an n-type layer by having deactivated p-type dopant atoms.

Abstract: Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.

Abstract: A device is provided that comprises a first layer deposited onto a second layer. The second layer comprises a lightly doped n-type or p-type semiconductor drift layer, and the first layer comprises a high-k material with a dielectric constant that is at least two times higher than the value of the second layer. A metal Schottky contact is formed on the first layer and a metal ohmic contact is formed on the second layer. Under reverse bias, the dielectric constant discontinuity leads to a very low electric field in the second layer, while the electron barrier created by the first layer stays almost flat. Under forward bias, electrons flow through the first layer, into the metal ohmic contact. For small values of conduction band offset or valence band offset between the first layer and the second layer, the device is expected to support efficient electron or hole transport.

Abstract: An example tunnel junction ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include a mesa structure having at least one of: an n-doped bottom contact region, a p-doped region, and a tunnel junction arranged in contact with the p-doped region. Additionally, a geometry of the mesa structure can be configured to increase respective efficiencies of extracting transverse-electric (TE) polarized light and transverse-magnetic (TM) polarized light from the tunnel junction UV LED. The mesa structure can be configured such that an emitted photon travels less than 10 ?m before reaching the inclined sidewall.

Abstract: Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.

Abstract: An example ultraviolet (UV) light emitting diode (LED) is described herein. The UV LED can include an n-doped contact region, an active region configured to emit UV light that is arranged between an n-doped region and a p-doped region, and a tunnel junction. The tunnel junction is arranged between the n-doped contact region and the p-doped region. In addition, the tunnel junction can include a heavily p-doped region, a degenerately n-doped region, and a semiconductor region arranged between the heavily p-doped region and the degenerately n-doped region. Each of the heavily p-doped region and the degenerately n-doped region has a gradually varied material energy bandgap to reduce respective depletion barriers within the heavily p-doped region and the degenerately n-doped region.

Abstract: This disclosure relates to a novel approach towards enhancing the threshold voltage of an enhancement-mode field-effect-transistor (E-mode FET) using doped or polarization-graded buffer layers and utilizing drain-connected field plates to engineer peak fields. Enhancement-mode field effect transistors (E-mode FETs) with doped buffer layers replacing conventional undoped buffer layers could enable larger threshold voltages, owing to higher capacitance from the back. These FETs with larger threshold voltages, however, would experience large operational electric fields near the drain contact. Described herein are embodiments of an E-mode FET further comprised of doped buffer layer(s) in the structure of the HEMT to enable larger positive threshold voltages, with optional one or more drain field plates that modify the electric field profile in the channel of the device and improve device breakdown characteristics.

Abstract: A nanowire comprises a polar semiconductor material that is compositionally graded along the nanowire from a first end to a second end to define a polarization doping profile along the nanowire from the first end to the second end. The polar semiconductor material may comprise a group IH-nitride semiconductor, such as an alloy of GaN and AlN, or an alloy of GaN and InN. Such nanowires may be formed by nucleating the first ends on a substrate, growing the nanowires by depositing polar semiconductor material on the nucleated first ends on a selected growth face, and compositionally grading the nanowires during growth to impart the polarization doping. The direction of the compositional grading may be reversed during the growing of the nanowires to reverse the type of the imparted polarization doping. In some embodiments, the reversing forms n/p or p/n junctions in the nanowires.

Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.