Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.

Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.

Abstract: A method and apparatus are provided for manufacturing an integrated circuit package assembly which includes a multichip package substrate having active and/or passive circuit devices embedded in one or more substrate core layers, a plurality of encapsulated integrated circuit devices attached to the multichip package substrate, and an optical waveguide fiber connected to a photonic integrated circuit device that is located in either the multichip package substrate or the encapsulated plurality of integrated circuit devices, where the optical waveguide fiber is optically coupled to an exposed fiber coupling region of the photonic integrated circuit device.

Abstract: An electronic device may include wireless circuitry having one or more antennas. An antenna ground for an antenna may be formed from two separate conductive ground structures coupled to each other via a conductive interconnect structure. A slot element may be formed in one of the conductive ground structures to reject signals at one or more victim frequencies resulting from spurious signals generated by a non-ohmic contact formed between the conductive interconnect structure and the one of the conductive ground structures. The conductive interconnect structure may overlap and excite the slot element, which serves as an ineffective radiator at the one or more victim frequencies.

Abstract: Semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. The semiconductor chips can be embedded within the molding compound. The semiconductor chips also can be adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels can be tailored to decrease warpage of the package as the semiconductor chip heats during use.

Abstract: Structures and methods of forming a thin-film electrolytic capacitor without the conductive polymer, thus improving the ESR performance as well as the reliability of the capacitor. Thin-film electrolytic capacitor structures include sintered anode, oxide deposition, conductive polymer, conductive metal inks, and metal cathodes.

Abstract: The present disclosure describes semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. In some examples, the semiconductor chips are embedded within the molding compound. In other examples, the semiconductor chips are adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels described herein can be tailored to decrease warpage of the package as the semiconductor chip heats during use.

Abstract: A semiconductor package substrate with embedded crack cessation structures and methods of forming the same is provided. Crack cessation structures include blind vias structures, through vias structures, and methods of forming the same are provided. Crack cessation structures may be formed by trenching of one or more structures, and deposition of metallic or insulative materials to form a crack cessation structures in the semiconductor package substrate core.

Abstract: A method and apparatus are provided for manufacturing a packaged assembly by attaching a plurality of multi-height integrated circuit components to an carrier or package substrate with embedded active and/or passive circuit elements and then forming an encapsulating molding compound to cover the multi-height integrated circuit components and then etching or grinding the encapsulating molding compound to expose each of the integrated circuit components at a planar heat dissipation surface so that a heat sink lid/cover can be formed with one or more thermal conductive layers to contact each of the exposed integrated circuit components, thereby enabling removal of heat from the integrated circuit components and the embedded active and/or passive circuit elements of the package substrate.

Abstract: A semiconductor package substrate with embedded passive devices and methods of forming the same is provided. Embedded passive devices include inductors and inductor modules and methods of forming the same are provided. Embedded inductors may be formed by deposition of magnetic core material, trenching of one or more channels, and placement of conductive wires to form an module embeddable in the semiconductor package substrate core. Provided are methods and apparatus for formation of embeddable pot-core, toroidal, and helical inductors.

Abstract: An electronic device may include wireless circuitry having one or more antennas. An antenna ground for an antenna may be formed from two separate conductive ground structures coupled to each other via a conductive interconnect structure. A slot element may be formed in one of the conductive ground structures to reject signals at one or more victim frequencies resulting from spurious signals generated by a non-ohmic contact formed between the conductive interconnect structure and the one of the conductive ground structures. The conductive interconnect structure may overlap and excite the slot element, which serves as an ineffective radiator at the one or more victim frequencies.

Abstract: In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.

Abstract: In one aspect, a capacitor or network of capacitors is/are provided for vertical power delivery in a package where the capacitor(s) is/are embedded in or forms the entirety of the package substrate core. In a second aspect, a plurality of thin-film capacitor structures are provided for implementing vertical power delivery in a package. In a third aspect a method is provided for fabricating hermetically sealed thin-film capacitors.

Abstract: An abradable sealing element comprises a substrate and a sealing structure. The sealing structure comprises one or more wall structures extending from the substrate and defining at least one open cell which is filled with abradable material. The one or more wall structures are formed by additive-layer, powder-fed, laser-weld deposition onto the substrate. The one or more wall structures are formed from nickel-based superalloy and constitute from about 10% to about 50% of the total volume of the sealing structure.

Abstract: The present disclosure describes semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. In some examples, the semiconductor chips are embedded within the molding compound. In other examples, the semiconductor chips are adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels described herein can be tailored to decrease warpage of the package as the semiconductor chip heats during use.

Abstract: Manufacturing a semiconductor chip package with optical fiber attach capability includes preparing a photonic integrated circuit by etching a v-groove in a front side fiber coupling region; assembling the photonic integrated circuit on an organic redistribution layer; etching the organic redistribution layer; and attaching an optical fiber to the front side fiber coupling region.

Abstract: An abradable sealing element comprises a substrate and a sealing structure. The sealing structure comprises one or more wall structures extending from the substrate and defining at least one open cell which is filled with abradable material. The one or more wall structures are formed by additive-layer, powder-fed, laser-weld deposition onto the substrate. The one or more wall structures are formed from nickel-based superalloy and constitute from about 10% to about 50% of the total volume of the sealing structure.

Abstract: Techniques for providing multi-antenna devices with increased antenna-to-antenna isolation as well as methods of operating and manufacturing the same are disclosed. A multi-antenna device may include a support structure, one or more radio devices coupled to a first antenna that is coupled to the support structure at a first location, a second antenna coupled to the support structure at a second location and communicatively coupled to the one or more radio devices, and a conductive structure coupled to the support structure so that it shifts an electric field null of the first antenna from an original location toward the second location during communications using the first antenna, thereby increasing isolation between the first antenna and the second antenna. The conductive structure may have a length of approximately one half of the wavelength (e.g., of 2.4 gigahertz or 5 gigahertz) of a frequency band used for the communications.

Abstract: Techniques for providing multi-antenna devices with increased antenna-to-antenna isolation as well as methods of operating and manufacturing the same are disclosed. A multi-antenna device may include a support structure, one or more radio devices coupled to a first antenna that is coupled to the support structure at a first location, a second antenna coupled to the support structure at a second location and communicatively coupled to the one or more radio devices, and a conductive structure coupled to the support structure so that it shifts an electric field null of the first antenna from an original location toward the second location during communications using the first antenna, thereby increasing isolation between the first antenna and the second antenna. The conductive structure may have a length of approximately one half of the wavelength (e.g., of 2.4 gigahertz or 5 gigahertz) of a frequency band used for the communications.