Patents by Inventor Siddharth S. Bhargav

Siddharth S. Bhargav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10963026
    Abstract: A digital integrated circuit comprising may include a digital sensor circuit that converts binary bit patterns of wires in a sub-circuit over a given time into a single integer value that represents the total activity of a sub-circuit, and a digital data processing circuit that receives multiple activity integer values from multiple digital sensors in multiple sub-circuits and logically combines the values or uses a lookup table to output a single integer value that represents the total activity of a larger sub-circuit.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: March 30, 2021
    Assignee: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Young H. Cho, Siddharth S. Bhargav, Andrew Goodney
  • Patent number: 10830800
    Abstract: In at least one aspect, a system is configured to use a mapping to determine per-component dynamic power consumed by components in a SoC during execution of instructions, the mapping translating consumed power per one or more instructions into consumed power per component based on a set of determined components (an adjusted set of proposed components) and derived weights, the set of proposed components having been generated to represent the components of the SoC and including a respective proposed component corresponding to each instruction, and the set of proposed components having been adjusted based on the derived weights being produced for the set of proposed components by at least combining two or more proposed components associated with two or more of the derived weights that converged to a shared value, and perform power and temperature management for the SoC in accordance with the determined per-component dynamic power consumption.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: November 10, 2020
    Assignee: University of Southern California
    Inventors: Young H. Cho, Siddharth S. Bhargav
  • Patent number: 10386395
    Abstract: Methods and systems, include, in one aspect, a system including: receiving a total static power indicating a static power dissipation from a complete circuit, wherein the circuit comprises a plurality of components; receiving dynamic power weights indicating changes in the static power dissipation from the complete circuit over time; applying an algorithm including the dynamic power weights to partition the total static power, based on the changes in the static power, into a summation of individual per-component static power values, wherein the per-component static power values indicate a decomposition of the static power dissipation from the complete circuit into separate amounts of per-component static power dissipation corresponding to each of the plurality of components; and processing the per-component static power to evaluate a performance of the circuit, the plurality of components, or both.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 20, 2019
    Assignee: University of Southern California
    Inventors: Young H. Cho, Siddharth S. Bhargav
  • Publication number: 20180088645
    Abstract: A digital integrated circuit comprising may include a digital sensor circuit that converts binary bit patterns of wires in a sub-circuit over a given time into a single integer value that represents the total activity of a sub-circuit, and a digital data processing circuit that receives multiple activity integer values from multiple digital sensors in multiple sub-circuits and logically combines the values or uses a lookup table to output a single integer value that represents the total activity of a larger sub-circuit.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 29, 2018
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Young H. Cho, Siddharth S. Bhargav, Andrew Goodney
  • Patent number: 9618547
    Abstract: Power consumed by a digital circuit that contains multiple sub-circuits may be computed. Each sub-circuit may include more than one transistor and have at least one input. A signal transition sensor may be connected to an input to each sub-circuit and configured to count the number of signal transitions at the input or to time the duration of a signal transition at the input. Weight information may be stored that is indicative of an amount of power that is being consumed by each sub-circuit based on a count that is counted by or a time duration that is timed by each signal transition sensor that is connected to an input of that sub-circuit. The amount of power being consumed by the digital circuit may be computed based on a count that is counted by or a time duration that is timed by each signal transition sensor and the weight information.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 11, 2017
    Assignee: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Young H. Cho, Siddharth S. Bhargav, Andrew Goodney
  • Publication number: 20140298049
    Abstract: A digital integrated circuit may include a digital data processing circuit having multiple signal lines that each go through signal transitions during operation of the digital data processing circuit. A digital counter circuit may count the combined number of signal transitions that take place on at least two of the multiple signal lines during operation of the digital circuit. A digital counter circuit may count the number of times a particular pattern of signal transitions takes place on at least one signal line during operation of the circuit. A computer program may receive information indicative of a composition of a digital integrated circuit, input vectors to the digital integrated circuit, and how much power is being consumed by the digital integrated circuit under each of the input vectors. The program may output information indicative of an amount of power being consumed by each of multiple, different sub-sections of the digital integrated circuit while responding to the input vectors.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Young H. Cho, Siddharth S. Bhargav, Andrew Goodney