Patents by Inventor Siddhartha DHAR

Siddhartha DHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378295
    Abstract: A transistor includes a semiconductor layer with a stack of a gate insulator and a conductive gate on the semiconductor layer. A thickness of the gate insulator is variable in a length direction of the transistor. The gate insulator includes a first region having a first thickness below a central region of the conductive gate. The gate insulator further includes a second region having a second thickness, greater than the first thickness, below an edge region of conductive gate.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 23, 2023
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Siddhartha DHAR, Stephane MONFRAY, Alain FLEURY, Franck JULIEN
  • Publication number: 20230335515
    Abstract: The present disclosure is directed to conductive structures that may be utilized in a radio-frequency (RF) switch. The embodiments of the conductive structures of the present disclosure are formed to balance the “on” resistance (Ron) and the “off” capacitance (Coff) such that the Ron·Coff value is optimized such that the conductive structures are relatively efficient as compared to conventional conductive structures within conventional RF switches. For example, the conductive structures include various metallization layers that are stacked on each other and spaced apart in a selected manner to balance the Ron and the Coff as to optimize the Ron·Coff figure of merit as a lower Ron·Coff is preferred.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 19, 2023
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics International N.V.
    Inventors: Siddhartha DHAR, Frederic GIANESELLO, Philippe CATHELIN
  • Publication number: 20220359435
    Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 10, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics International N.V.
    Inventors: Stephane MONFRAY, Siddhartha DHAR, Alain FLEURY