Patents by Inventor Siddhartha Gopal Krishna

Siddhartha Gopal Krishna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12113521
    Abstract: A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: October 8, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Siddhartha Gopal Krishna, Priyank Anand, Ganapathi Hegde
  • Patent number: 12081159
    Abstract: A motor control system and method for controlling a brushed direct current (BDC) motor using a feedback loop based on a corrected ripple count. Motor control circuitry, for example implemented in digital logic such as a microcontroller, receives a coil current signal and a motor voltage signal. Discontinuities in the coil current signal, such as caused by commutation of the BDC motor, are counted to generate a ripple count. An observer function derives an angular frequency model estimate for the values of the coil current and motor voltage signals using a computational model for the motor. A corrected ripple count is generated based on a comparison of a commutation angle of the motor with an angular position based on the angular frequency model estimate over a time interval between discontinuity pulses. A motor drive signal is adjusted based on the corrected ripple count.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: September 3, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkata Naresh Kotikelapudi, Kaushik Alwala, David Magee, James Lockridge, Siddhartha Gopal Krishna
  • Patent number: 11949364
    Abstract: A method for controlling a stepper motor includes calculating a duty cycle of a current provided to the stepper motor and comparing a difference, between the calculated duty cycle and a base duty cycle of current provided to the stepper motor under a base load condition, to a reference duty cycle value. The method also includes adjusting a peak current level of the current provided to the stepper motor responsive to the comparison.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: April 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Venkata Naresh Kotikelapudi, Ganapathi Shankar Krishnamurthy, Laxman Sreekumar, Siddhartha Gopal Krishna
  • Patent number: 11923799
    Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Siddhartha Gopal Krishna, Priyank Anand, Ganapathi Hegde
  • Publication number: 20230253898
    Abstract: A motor control system and method for controlling a brushed direct current (BDC) motor using a feedback loop based on a corrected ripple count. Motor control circuitry, for example implemented in digital logic such as a microcontroller, receives a coil current signal and a motor voltage signal. Discontinuities in the coil current signal, such as caused by commutation of the BDC motor, are counted to generate a ripple count. An observer function derives an angular frequency model estimate for the values of the coil current and motor voltage signals using a computational model for the motor. A corrected ripple count is generated based on a comparison of a commutation angle of the motor with an angular position based on the angular frequency model estimate over a time interval between discontinuity pulses. A motor drive signal is adjusted based on the corrected ripple count.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Inventors: Venkata Naresh Kotikelapudi, Kaushik Alwala, David Magee, James Lockridge, Siddhartha Gopal Krishna
  • Patent number: 11646684
    Abstract: A stepper motor driver includes an H-bridge including first and second outputs. The H-bridge includes a low-side transistor coupled between the first output and a ground. A reference current circuit is configured to produce a reference current. The reference current circuit has a reference output. An averager circuit includes an input and output. The input of the averager circuit is coupled to the first output of the H-bridge. A comparator includes first and second comparator inputs. The first input of the comparator is coupled to the output of the average circuit and the second input of the comparator is coupled to the reference output.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 9, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnamurthy Shankar, Venkata Naresh Kotikelapudi, Siddhartha Gopal Krishna
  • Publication number: 20230097035
    Abstract: A method for controlling a stepper motor includes calculating a duty cycle of a current provided to the stepper motor and comparing a difference, between the calculated duty cycle and a base duty cycle of current provided to the stepper motor under a base load condition, to a reference duty cycle value. The method also includes adjusting a peak current level of the current provided to the stepper motor responsive to the comparison.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Venkata Naresh KOTIKELAPUDI, Ganapathi Shankar KRISHNAMURTHY, Laxman SREEKUMAR, Siddhartha GOPAL KRISHNA
  • Publication number: 20230044791
    Abstract: An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Siddhartha Gopal Krishna, Priyank Anand, Ganapathi Hegde
  • Publication number: 20230039198
    Abstract: A control circuit regulates the propagation delay of a field effect transistor (FET) before the FET transitions to the Miller region by applying a pre-charge current for a fixed duration to the gates of the FET. After the fixed duration, the current is reduced to a lower drive current level which is based on a desired output voltage slew rate. After the FET transitions to the Miller region, the output voltage slews down in accordance with the output voltage slew rate. By regulating the slew-rate of the output voltage in the Miller region and regulating the propagation delay of the FET prior to the Miller region, the control circuit reduces electromagnetic interference (EMI) caused by the switching of the FET, thereby improving electromagnetic compatibility (EMC) of switch mode driver systems without increasing the propagation delay of the FET.
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Siddhartha Gopal Krishna, Priyank Anand, Ganapathi Hegde
  • Patent number: 11469586
    Abstract: A circuit includes a first transistor, a second transistor, and a sense transistor. The first current terminals of the first and second transistors are coupled together at a power supply node. The control terminals of the second and third transistors are coupled together. The second current terminals of the first, second, and third transistors are coupled together. The sense resistor is coupled between the first current terminals of the first and second transistors and the first current terminal of the third transistor. The first and second transistors are configured such that during a first mode of operation, current to a load flows through the first and second transistors, and during a second mode of operation, current to a load is discontinued through the first transistor yet flows through the second transistor.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: October 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Ojha, Krishnamurthy Shankar, Divyasree J, Siddhartha Gopal Krishna, Sarangan Thirumavalavan
  • Patent number: 11255920
    Abstract: A circuit includes an input terminal, a first transistor, a second transistor, a comparator, a voltage reference circuit, and a control circuit. The first transistor includes a first terminal coupled to the input terminal. The second transistor includes a first terminal coupled to the input terminal. The comparator includes a first terminal coupled to the input terminal. The voltage reference circuit is coupled to a second terminal of the comparator. The control circuit includes an input, a first output, and a second output. The input is coupled to an output of the comparator. The first output is coupled to a second terminal of the first transistor. The second output is coupled to a second terminal of the second transistor.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 22, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Ashish Ojha, Siddhartha Gopal Krishna, Divyasree J, Krishnamurthy Shankar, Venkata Naresh Kotikelapudi
  • Publication number: 20210247462
    Abstract: A circuit includes an input terminal, a first transistor, a second transistor, a comparator, a voltage reference circuit, and a control circuit. The first transistor includes a first terminal coupled to the input terminal. The second transistor includes a first terminal coupled to the input terminal. The comparator includes a first terminal coupled to the input terminal. The voltage reference circuit is coupled to a second terminal of the comparator. The control circuit includes an input, a first output, and a second output. The input is coupled to an output of the comparator. The first output is coupled to a second terminal of the first transistor. The second output is coupled to a second terminal of the second transistor.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Ashish OJHA, Siddhartha GOPAL KRISHNA, Divyasree J, Krishnamurthy SHANKAR, Venkata Naresh KOTIKELAPUDI
  • Publication number: 20210050808
    Abstract: A stepper motor driver includes an H-bridge including first and second outputs. The H-bridge includes a low-side transistor coupled between the first output and a ground. A reference current circuit is configured to produce a reference current. The reference current circuit has a reference output. An averager circuit includes an input and output. The input of the averager circuit is coupled to the first output of the H-bridge. A comparator includes first and second comparator inputs. The first input of the comparator is coupled to the output of the average circuit and the second input of the comparator is coupled to the reference output.
    Type: Application
    Filed: July 20, 2020
    Publication date: February 18, 2021
    Inventors: Krishnamurthy SHANKAR, Venkata Naresh KOTIKELAPUDI, Siddhartha GOPAL KRISHNA
  • Publication number: 20200389008
    Abstract: A circuit includes a first transistor, a second transistor, and a sense transistor. The first current terminals of the first and second transistors are coupled together at a power supply node. The control terminals of the second and third transistors are coupled together. The second current terminals of the first, second, and third transistors are coupled together. The sense resistor is coupled between the first current terminals of the first and second transistors and the first current terminal of the third transistor. The first and second transistors are configured such that during a first mode of operation, current to a load flows through the first and second transistors, and during a second mode of operation, current to a load is discontinued through the first transistor yet flows through the second transistor.
    Type: Application
    Filed: April 30, 2020
    Publication date: December 10, 2020
    Inventors: Ashish OJHA, Krishnamurthy SHANKAR, Divyasree J., Siddhartha GOPAL KRISHNA, Sarangan THIRUMAVALAVAN
  • Patent number: 9643558
    Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: May 9, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Siddhartha Gopal Krishna, Russell J. Lynch, Vikram Varma
  • Patent number: 9588155
    Abstract: Threshold detection for load current on a bus involves generating an output current representative of the load current using a transconductance circuit, sampling the output current during a quiescent phase of the bus to produce a sample current, generating a compensation current that is proportional to the transconductance gain associated with the transconductance circuit, where the compensation current is a function of the sample current, combining the output current, the sample current, the compensation current, and a reference current representative of a threshold value for the load current to produce a combined current, and using a discriminator during an active phase of the bus to output a first value when the sum current exceeds the threshold value and a second value when the combined current is less than the threshold value.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: March 7, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Siddhartha Gopal Krishna, Ramji Gupta
  • Publication number: 20160236637
    Abstract: A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Inventors: SIDDHARTHA GOPAL KRISHNA, Russell J. Lynch, Vikram Varma
  • Patent number: 9353017
    Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 31, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Siddhartha Gopal Krishna, Vikram Varma
  • Publication number: 20160109489
    Abstract: Threshold detection for load current on a bus involves generating an output current representative of the load current using a transconductance circuit, sampling the output current during a quiescent phase of the bus to produce a sample current, generating a compensation current that is proportional to the transconductance gain associated with the transconductance circuit, where the compensation current is a function of the sample current, combining the output current, the sample current, the compensation current, and a reference current representative of a threshold value for the load current to produce a combined current, and using a discriminator during an active phase of the bus to output a first value when the sum current exceeds the threshold value and a second value when the combined current is less than the threshold value.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 21, 2016
    Inventors: Siddhartha Gopal Krishna, Ramji Gupta
  • Publication number: 20150362942
    Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Siddhartha Gopal Krishna, Vikram Varma