Patents by Inventor Siddhartha Kumar Panda

Siddhartha Kumar Panda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11106361
    Abstract: Technologies for quality of service (QoS) management include a computing device having a physical storage volume and multiple processor cores. A management thread reads I/O counters that are each associated with a logical volume and a processor core. The logical volumes are backed by the physical storage volume. The management thread configures stop bits as a function of the I/O counters and multiple QoS parameters. Each stop bit is associated with a logical volume and a processor core. The QoS parameters include minimum guaranteed bandwidth and optional maximum allowed bandwidth for each logical volume. A worker thread reads the stop bit associated with a logical volume and a processor core, accesses the logical volume if the stop bit is not set, and updates the I/O counter associated with the logical volume and the processor core in response to accessing the logical volume. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Sujoy Sen, Siddhartha Kumar Panda, Jayaraj Puthenpurackal Rajappan, Kunal Sablok, Ramkumar Venkatachalam
  • Publication number: 20200371689
    Abstract: Technologies for quality of service (QoS) management include a computing device having a physical storage volume and multiple processor cores. A management thread reads I/O counters that are each associated with a logical volume and a processor core. The logical volumes are backed by the physical storage volume. The management thread configures stop bits as a function of the I/O counters and multiple QoS parameters. Each stop bit is associated with a logical volume and a processor core. The QoS parameters include minimum guaranteed bandwidth and optional maximum allowed bandwidth for each logical volume. A worker thread reads the stop bit associated with a logical volume and a processor core, accesses the logical volume if the stop bit is not set, and updates the I/O counter associated with the logical volume and the processor core in response to accessing the logical volume. Other embodiments are described and claimed.
    Type: Application
    Filed: May 20, 2019
    Publication date: November 26, 2020
    Inventors: Sujoy Sen, Siddhartha Kumar Panda, Jayaraj Puthenpurackal Rajappan, Kunal Sablok, Ramkumar Venkatachalam
  • Patent number: 10534541
    Abstract: Method and apparatus for asynchronous discovery of processing and storage nodes coupled via an expander switch in a fabric. In some embodiments, an initiator device operates as a processing node to transfer data to and from a non-volatile memory (NVM) of a target device at a storage node. One of the initiator or target devices is activated prior to the other device. The second activated device broadcasts a discovery command responsive to the activation of the second activated device and prior to receipt of a request for the discovery command from the first activated device. The first activated device processes the discovery command to establish an I/O communication link between the first activated device and the second activated device. The discovery command may include a non-volatile memory express (NVMe) controller list, and the NVM may be arranged as one or more NVMe namespaces.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Seagate Technology LLC
    Inventors: Mark Ish, Siddhartha Kumar Panda, Dileep Kumar Sharma, Durga Prasad Bhattarai
  • Patent number: 10310975
    Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: June 4, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, Mark Ish, Siddhartha Kumar Panda, Bagavathy Raj Arunachalam
  • Publication number: 20180081558
    Abstract: Method and apparatus for asynchronous discovery of processing and storage nodes coupled via an expander switch in a fabric. In some embodiments, an initiator device operates as a processing node to transfer data to and from a non-volatile memory (NVM) of a target device at a storage node. One of the initiator or target devices is activated prior to the other device. The second activated device broadcasts a discovery command responsive to the activation of the second activated device and prior to receipt of a request for the discovery command from the first activated device. The first activated device processes the discovery command to establish an I/O communication link between the first activated device and the second activated device. The discovery command may include a non-volatile memory express (NVMe) controller list, and the NVM may be arranged as one or more NVMe namespaces.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 22, 2018
    Inventors: Mark Ish, Siddhartha Kumar Panda, Dileep Kumar Sharma, Durga Prasad Bhattarai
  • Publication number: 20170329707
    Abstract: The disclosed technology provides for selection of a subset of available non-volatile memory devices in an array to receive a dirty cache data of a volatile cache responsive to detection of a power failure. In one implementation, the selection of the non-volatile memory devices is based on one or more predictive power parameters usable to estimate a time remaining during which a reserve power supply can support a cache offload to the selected subset of devices.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, Mark Ish, Siddhartha Kumar Panda, Bagavathy Raj Arunachalam
  • Patent number: 9274713
    Abstract: A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 1, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Horia Simionescu, Siddhartha Kumar Panda, Kunal Sablok, Kapil Sundrani
  • Publication number: 20150286438
    Abstract: A storage controller coupled to a host computer is dynamically configured by a device driver executing in the host computer. The storage controller manages a logical volume for the host using a set of flash-based storage devices arranged as a redundant array of inexpensive disks (RAID). The device driver identifies a RAID type for the logical volume and a queue depth from a stream of I/O commands. For a logical volume in RAID 0, the device driver compares the queue depth to a threshold value and configures the storage controller to process the stream of I/O commands with a first path or an alternative path based on a result of the comparison. For a logical volume in RAID 5, the device driver performs a similar comparison and uses the result to direct the storage controller to use a write back or a write through mode of operation.
    Type: Application
    Filed: May 8, 2014
    Publication date: October 8, 2015
    Applicant: LSI Corporation
    Inventors: Horia Simionescu, Siddhartha Kumar Panda, Kunal Sablok, Kapil Sundrani
  • Publication number: 20140258595
    Abstract: A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logical devices and exposed to a resource allocator. A core caching algorithm executes in the guest virtual machine. As new virtual machines are added under the management of the virtual machine monitor, existing virtual machines are prompted to relinquish a portion of the cache store allocated for use by the respective existing machines. The relinquished cache is allocated to the new machine. Similarly, if a virtual machine is shutdown or migrated to a new host system, the cache capacity allocated to the virtual machine is redistributed among the remaining virtual machines being managed by the virtual machine monitor.
    Type: Application
    Filed: August 15, 2013
    Publication date: September 11, 2014
    Applicant: LSI Corporation
    Inventors: Pradeep Radhakrishna Venkatesha, Siddhartha Kumar Panda, Parag R. Maharana, Luca Bert
  • Patent number: 8799631
    Abstract: Disclosed is a microprocessor based system with a dynamically selectable Operating System that is capable of providing unique operating systems based upon current hardware states without user intervention. The system will determine the current state of the system and select from a plurality of operating systems the best operating system to load. In normal operating conditions the system will select the most full-featured and robust operating system. If, for example, the system loses alternating-current power, the system will shutdown, reboot, and automatically select an operating system with very limited capabilities and limited power consumption to allow the system to retrieve important data from the cache and store the data to a data storage device.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: August 5, 2014
    Assignee: LSi Corporation
    Inventors: Ashish Batwara, James K. Sandwell, Siddhartha Kumar Panda, Sisir Kumar Dash
  • Publication number: 20130290601
    Abstract: An I/O scheduler and a method for scheduling I/O requests to a solid-state drive (SSD) is disclosed. The I/O scheduler in accordance with the present disclosure bundles the write requests in such a form that the write requests in each bundle goes into one SSD block. Bundling the write requests in accordance with the present disclosure reduces write amplification and increases system performance. The I/O scheduler in accordance with the present disclosure also helps increasing the life of the SSDs.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Applicant: LSI CORPORATION
    Inventors: Kunal Sablok, Siddhartha Kumar Panda