Abstract: Systems, apparatuses and methods may provide for technology that determines a vocabulary based on EDA tool terminologies and/or a natural language, queries and recommends, by a plurality of virtual agents, actions based on a design state and the vocabulary, wherein the plurality of agents is to include a tool agent and a designer agent, and executes a set of modifications to the design state in accordance with a collaboration between the plurality of agents. The technology may also convert a first user query from a first format to a second format, wherein the first format is incompatible with a trained AI model of a hardware architecture and the second format is compatible with the trained AI model, generate one or more predictions from the trained AI model based on the converted first user query, and select a subset of recommendations from a set of candidate architectures based on the prediction(s).

Abstract: When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.

Abstract: Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.

Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.

Abstract: A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML system. Thereafter, a detailed route of the circuit design is performed by a detailed router. A label associated with each Gcell in the circuit design is delivered to the ML system from the detailed route. The ML system is trained using the first and second list of features and the labels.

Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.

Abstract: Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

Abstract: When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.

Abstract: Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.

Abstract: An electronic data tablet has a controller and transition manager. The controller is to store in a memory of the tablet virtual configuration space information for a peripheral device of a computer, and the transition manager is to control the controller to operate in a first mode and a second mode. The virtual configuration space information is stored in the tablet memory when the first mode is to be switched to the second mode. When the second mode is switched to the first mode, the virtual configuration space information is accessed to control recognition of the peripheral device of the computer without performing a re-scanning operation.

Abstract: Embodiments of systems, apparatuses, and methods for virtualizing a powered-down input/output device are disclosed. In one embodiment, an apparatus includes a storage location and a decoder. The storage location is to store an indication that an input/output device is inaccessible. The decoder is to decode a configuration transaction directed to the input/output device and redirect the configuration transaction to an other target if the contents of the first storage location indicate that the input/output device is inaccessible.

Abstract: Techniques are described that track the lines and pixels in a frame buffer in the host system that are being modified and transmit these modified scan lines and modified pixel locations to the self refresh display instead of entire contents of the frame buffer. The graphics adapter informs the self refresh display of the modified scan lines or pixel information and then sends the pixel data over the communications channel to the display. Custom codes can be used to identify and transmit modified scan lines and pixels to the self refresh display logic.

Abstract: An electronic data tablet has a controller and transition manager. The controller is to store in a memory of the tablet virtual configuration space information for a peripheral device of a computer, and the transition manager is to control the controller to operate in a first mode and a second mode. The virtual configuration space information is stored in the tablet memory when the first mode is to be switched to the second mode. When the second mode is switched to the first mode, the virtual configuration space information is accessed to control recognition of the peripheral device of the computer without performing a re-scanning operation.

Abstract: An electronic device comprises at least two graphics processors, referred to herein as an integrated graphics processor and a discrete graphics processor. In some circumstances, the device may be switched between the integrated graphics processor and the discrete graphics processor. In some embodiments, techniques are implemented to lock temporarily the screen display on the output of a controller while the device executes a switch between graphics processors, thereby eliminating, or at least reducing, the presence of a blank output display on the electronic device. Other embodiments may be described.

Abstract: Techniques are described that track the lines and pixels in a frame buffer in the host system that are being modified and transmit these modified scan lines and modified pixel locations to the self refresh display instead of entire contents of the frame buffer. The graphics adapter informs the self refresh display of the modified scan lines or pixel information and then sends the pixel data over the communications channel to the display. Custom codes can be used to identify and transmit modified scan lines and pixels to the self refresh display logic.

Abstract: Embodiments of systems, apparatuses, and methods for virtualizing a powered-down input/output device are disclosed. In one embodiment, an apparatus includes a storage location and a decoder. The storage location is to store an indication that an input/output device is inaccessible. The decoder is to decode a configuration transaction directed to the input/output device and redirect the configuration transaction to an other target if the contents of the first storage location indicate that the input/output device is inaccessible.

Abstract: An electronic device comprises at least two graphics processors, referred to herein as an integrated graphics processor and a discrete graphics processor. In some circumstances, the device may be switched between the integrated graphics processor and the discrete graphics processor. In some embodiments, techniques are implemented to lock temporarily the screen display on the output of a controller while the device executes a switch between graphics processors, thereby eliminating, or at least reducing, the presence of a blank output display on the electronic device. Other embodiments may be described.