Patents by Inventor Siddhartha Panda
Siddhartha Panda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140328373Abstract: Techniques described herein generally relate to methods of manufacturing devices and systems including devices including a substrate with a surface, a conductive polymer film arranged on the surface of the substrate, wherein the conductive polymer film has one or more temperature reactive characteristics, and a pair of electrodes coupled to the polymer film, wherein the pair of electrodes are configured to communicate electrical signals to the conductive polymer film effective to measure the one or more temperature reactive characteristics. The conductive polymer film may be arranged on the surface of the substrate such that a thickness and dopant ratio of the conductive polymer film on the substrate is configurable.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Inventors: SIDDHARTHA PANDA, HAKEEM ABRAR AHMED
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Patent number: 8783948Abstract: Techniques described herein generally relate to methods of manufacturing devices and systems including devices including a substrate with a surface, a conductive polymer film arranged on the surface of the substrate, wherein the conductive polymer film has one or more temperature reactive characteristics, and a pair of electrodes coupled to the polymer film, wherein the pair of electrodes are configured to communicate electrical signals to the conductive polymer film effective to measure the one or more temperature reactive characteristics. The conductive polymer film may be arranged on the surface of the substrate such that a thickness and dopant ratio of the conductive polymer film on the substrate is configurable.Type: GrantFiled: November 9, 2010Date of Patent: July 22, 2014Assignee: Indian Institute of Technology KanpurInventors: Siddhartha Panda, Hakeem Abrar Ahmed
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Patent number: 8492803Abstract: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.Type: GrantFiled: November 20, 2008Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Wesley C. Natzle, Siddhartha Panda, Brian L. Tessier
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Publication number: 20120263209Abstract: Techniques described herein generally relate to methods of manufacturing devices and systems including devices including a substrate with a surface, a conductive polymer film arranged on the surface of the substrate, wherein the conductive polymer film has one or more temperature reactive characteristics, and a pair of electrodes coupled to the polymer film, wherein the pair of electrodes are configured to communicate electrical signals to the conductive polymer film effective to measure the one or more temperature reactive characteristics. The conductive polymer film may be arranged on the surface of the substrate such that a thickness and dopant ratio of the conductive polymer film on the substrate is configurable.Type: ApplicationFiled: November 9, 2010Publication date: October 18, 2012Applicant: INDIAN INSTITUTE OF TECHNOLOGY KANPURInventors: Siddhartha Panda, Hakeem Abrar Ahmed
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Patent number: 8048325Abstract: A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH3), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NH3 and a hydrocarbon gas such as at least one of C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10, and C6H12. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH3), and a passivation gas.Type: GrantFiled: January 7, 2008Date of Patent: November 1, 2011Assignee: Tokyo Electron LimitedInventors: Vaidyanathan Balasubramaniam, Koichiro Inazawa, Rie Inazawa, Rich Wise, Arpan Mahorawala, Siddhartha Panda
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Patent number: 7977185Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.Type: GrantFiled: November 22, 2005Date of Patent: July 12, 2011Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
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Patent number: 7863197Abstract: A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.Type: GrantFiled: January 9, 2006Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Judson R. Holt, Qiqing C. Ouyang, Siddhartha Panda
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Patent number: 7776695Abstract: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.Type: GrantFiled: January 9, 2006Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: John C. Arnold, Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha, Siddhartha Panda, Brian L. Tessier, Richard Wise
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Publication number: 20100187636Abstract: A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.Type: ApplicationFiled: April 6, 2010Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Haining S. Yang, Siddhartha Panda
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Patent number: 7754615Abstract: A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode surrounding the second electrode, and the DC current is monitored to determine the endpoint of the etching process. The DC current is affected by the impedance of the plasma, and therefore responds to many variations including, for example, the plasma density, electron/ion flux to exposed surfaces, the electron temperature, etc.Type: GrantFiled: July 31, 2006Date of Patent: July 13, 2010Assignees: Tokyo Electron Limited, International Business Machines Corporation (“IBM ”)Inventors: Siddhartha Panda, Richard Wise, Lee Chen, Michael Sievers
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Patent number: 7709317Abstract: A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.Type: GrantFiled: November 14, 2005Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Haining S. Yang, Siddhartha Panda
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Patent number: 7687829Abstract: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.Type: GrantFiled: June 23, 2008Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Judson R. Holt, Meikei Ieong, Qiqing C. Ouyang, Siddhartha Panda
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Patent number: 7645656Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.Type: GrantFiled: August 10, 2006Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Sang-Hyun Oh, Siddhartha Panda, Werner A. Rausch, Tsutomu Sato, Henry K. Utomo
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Patent number: 7645356Abstract: A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.Type: GrantFiled: November 25, 2003Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: Siddhartha Panda, Richard S. Wise
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Publication number: 20090159934Abstract: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.Type: ApplicationFiled: November 20, 2008Publication date: June 25, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky S. Amos, Wesley C. Natzle, Siddhartha Panda, Brian L. Tessier
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Patent number: 7525161Abstract: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.Type: GrantFiled: January 31, 2007Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Meikei Ieong, Xiao Hu Liu, Qiqing Christine Ouyang, Siddhartha Panda, Haizhou Yin
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Publication number: 20090104776Abstract: A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.Type: ApplicationFiled: October 18, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Dobuzinsky, Johnathan E. Faltermeier, Naoyoshi Kusaba, Joyce C. Liu, Munir D. Naeem, Siddhartha Panda, Richard S. Wise, Hongwen Yan
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Patent number: 7459382Abstract: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.Type: GrantFiled: March 24, 2006Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Wesley C. Natzle, Siddhartha Panda, Brian L. Tessier
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Patent number: 7442618Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.Type: GrantFiled: July 16, 2005Date of Patent: October 28, 2008Assignees: Chartered Semiconductor Manufacturing, LtdInventors: Yung Fu Chong, Brian Joseph Greene, Siddhartha Panda, Nivo Rovedo
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Publication number: 20080258180Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.Type: ApplicationFiled: January 9, 2006Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huajie Chen, Dureseti Chidambarrao, Judson R. Holt, Qiqing Ouyang, Siddhartha Panda