Abstract: Technology for data dependent control of a delay between a data strobe signal and data signals. The delay may be adjusted to compensate for data dependent impacts on propagation delays in an unmatched data in path and data strobe path. The delay between the data strobe signal and data signals may be adjusted based on a number of toggles in data to be sent to a memory die.

Abstract: In a non-volatile memory device, the amount of delay along an I/O path for transferring received data to a sense amplifier and the amount of delay along a clock path to the sense amplifier can differ. To compensate for this differential delay, a replica of each of the I/O path and the clock path can be included on the memory device. The replica circuits can be used to determine this differential delay between the two paths. To compensate for this difference, an additional delay can be introduced into one or both of the paths, such as in the I/O path, so that any difference in propagations times can be reduced.

Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.

Abstract: A circuit for detecting an error in a byte of data transmitted over a channel includes a controller having a first DBI encoder configured to perform a first DBI encoding on a received byte of data. The circuit also includes a channel configured to receive the encoded byte from the controller. The circuit also includes a non-volatile memory having a second DBI encoder and configured to (1) perform a second DBI encoding on the encoded byte received over the channel, (2) check a DBI flag for the byte after the second DBI encoding, and (3) determine that the byte of data contains an error when the DBI flag after the second DBI encoding is 1. If the byte contains an error then it can be concluded that the channel contains a defect. In case of an error a write operation to memory core can be stopped.

Abstract: The disclosure provides circuits and methods for increasing NAND input/output (I/O) bandwidth during read/write operations. The method includes transmitting a clock signal between a controller I/O circuit and a memory I/O circuit along a read enable bus, transmitting 8 bits of data along an I/O bus, and transmitting 2 bits of data along a data strobe signal (DQS) bus. Transmitting 2 bits of data along the DQS bus includes transmitting a first DQS data signal along the DQS bus and transmitting a first inverse DQS data signal along the DQS bus.

Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.