Patents by Inventor Siddhesh Mhambrey

Siddhesh Mhambrey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low complexity out-of-order issue logic using static circuits
    Patent number: 9740494
    Abstract: Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 22, 2017
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Siddhesh Mhambrey, Satendra Kumar Maurya
  • LOW COMPLEXITY OUT-OF-ORDER ISSUE LOGIC USING STATIC CIRCUITS
    Publication number: 20120278593
    Abstract: Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.
    Type: Application
    Filed: April 30, 2012
    Publication date: November 1, 2012
    Applicant: Arizona Technology Enterprises, LLC
    Inventors: Lawrence T. Clark, Siddhesh Mhambrey, Satendra Kumar Maurya