Patents by Inventor Sidharth

Sidharth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260179635
    Abstract: Systems and methods performed by a processor of a computing device for online audio enhancement. Embodiments may include encoding an input audio signal by an encoder of a deep state-space autoencoder based in part on executing a first state-space model (SSM) generating an encoded signal, decoding a signal derived in part from the encoded signal by a decoder of the deep state-space autoencoder based in part on executing a second SSM to generate a decoded signal, and generating an enhanced output signal based in part on executing a third SSM based on the decoded signal.
    Type: Application
    Filed: December 22, 2025
    Publication date: June 25, 2026
    Inventors: Yan Ru PEI, Ritik SHRIVASTAVA, SIDHARTH
  • Patent number: 6461879
    Abstract: In the testing of one or more die as part of a semiconductor wafer, electrical testing of an unstressed die of a wafer is undertaken. The die of the wafer is then physically stressed to a first stressed state, and electrical testing is undertaken thereon. The die of the wafer is then physically stressed to a second stressed state, and electrical testing is again undertaken on the die as it is in its second stressed state. The results of the tests are compared and extrapolated to indicate electrical performance of the die in other physically stressed states. A relatively simple tool is provided for use in performing in this method in an effective and rapid manner.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: October 8, 2002
    Assignee: Advanced Micro Devices Inc.
    Inventors: Richard C. Blish, II, Sidharth
  • Patent number: 6015280
    Abstract: Methodology for reducing the warpage in thinly packaged electrical components, and electrical components packaged according to the method. The method taught herein is to make the gates themselves compliant, or flexible, thereby absorbing the stresses which would otherwise cause package deformation, including warpage. The present invention teaches two preferred embodiments for attaining this novel solution, including the adoption of wide, thin gates and the use of serpentine gates.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: January 18, 2000
    Assignee: Advanced Micro Devices
    Inventors: Richard C. Blish, II, Sidharth