Patents by Inventor Sidhartha Gupta

Sidhartha Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147713
    Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 2, 2024
    Inventors: Lifang Xu, Sidhartha Gupta, Kar Wui Thong, Harsh Narendarakumar Jain
  • Publication number: 20240099006
    Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Sidhartha Gupta, Anilkumar Chandolu, S M Istiaque Hossain
  • Publication number: 20240098993
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Andrew Li, Sidhartha Gupta, Adam W. Saxler
  • Publication number: 20240099007
    Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
  • Publication number: 20240081076
    Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Sidhartha Gupta, Matthew J. King, Jiewei Chen, Yi Hu
  • Publication number: 20240071918
    Abstract: A microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. The stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. At least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. The additional steps have greater tread widths in the first direction than the steps. Conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. Memory devices and electronic systems are also described.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Lifang Xu, Sidhartha Gupta, Indra V. Chary, Richard J. Hill, Umberto Maria Meotto
  • Publication number: 20240074201
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Matthew J. King, Albert Fayrushin, Sidhartha Gupta, Jun Fujiki, Masashi Yoshida, Yiping Wang, Taehyun Kim, Arun Kumar Dhayalan
  • Patent number: 11903196
    Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
  • Patent number: 11869841
    Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having arcuate horizontal boundaries defining additional horizontal widths varying from the first horizontal width proximate the lower portion to a relatively larger horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sidhartha Gupta
  • Patent number: 11856763
    Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Sidhartha Gupta, Kar Wui Thong, Harsh Narendrakumar Jain
  • Patent number: 11849581
    Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, Anilkumar Chandolu, S M Istiaque Hossain
  • Publication number: 20230276624
    Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Inventors: Pankaj Sharma, Naveen Kaushik, Sidhartha Gupta
  • Publication number: 20230187346
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Naveen Kaushik, Sidhartha Gupta, Pankaj Sharma, Haitao Liu
  • Publication number: 20230139457
    Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 4, 2023
    Inventors: Sidhartha Gupta, Anilkumar Chandolu
  • Patent number: 11605589
    Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Naveen Kaushik, Sidhartha Gupta, Pankaj Sharma, Haitao Liu
  • Publication number: 20230039621
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, Naveen Kaushik, Pankaj Sharma
  • Publication number: 20230045353
    Abstract: A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Inventors: S M Istiaque Hossain, Indra V. Chary, Anilkumar Chandolu, Sidhartha Gupta, Shuangqiang Luo
  • Publication number: 20220415917
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 29, 2022
    Inventors: Daniel Billingsley, Matthew J. King, Jordan D. Greenlee, Yongjun J. Hu, Tom George, Amritesh Rai, Sidhartha Gupta, Kyle A. Ritter
  • Patent number: 11527546
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Matthew J. King, Jordan D. Greenlee, Yongjun J. Hu, Tom George, Amritesh Rai, Sidhartha Gupta, Kyle A. Ritter
  • Publication number: 20220384242
    Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Sidhartha Gupta, David Ross Economy, Richard J. Hill, Kyle A. Ritter, Naveen Kaushik