Abstract: A system-on-chip comprises processing circuitry to process input data to generate output data, and power management circuitry to control power management policy for at least a portion of the system-on-chip. The power management circuitry controls the power management policy depending on metadata indicative of a property of the input data to be processed by the processing circuitry.

Abstract: A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers.

Abstract: A method and circuit for a data processing system provide a hardware accelerator repeat control instruction (402A) which is executed with a hardware accelerator instruction (402B) to extract and latch repeat parameters from the hardware accelerator repeat control instruction, such as a repeat count value (RPT_CNT), a source address offset value (ADDR_INCR0), and a destination address offset value (ADDR_INCR1), and to generate a command to the hardware accelerator (205) to execute the hardware accelerator instruction a specified plurality of times based on instruction parameters from the hardware accelerator instruction by using the repeat count value to track how many times the hardware accelerator instruction is executed and by automatically generating, at each execution of the hardware accelerator instruction, additional source and destination addresses for the hardware accelerator from the repeat parameters until the hardware accelerator instruction has been executed the specified plurality of times by the

Abstract: A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers.

Abstract: A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.

Abstract: An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.

Abstract: An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.