Patents by Inventor Sidhesh Patel

Sidhesh Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Staged scenario generation
    Patent number: 8423933
    Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 16, 2013
    Assignee: LSI Corporation
    Inventors: Sidhesh Patel, Prakash Bodhak
  • Staged Scenario Generation
    Publication number: 20110239171
    Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
    Type: Application
    Filed: June 1, 2011
    Publication date: September 29, 2011
    Applicant: LSI CORPORATION
    Inventors: Sidhesh Patel, Prakash Bodhak
  • Staged scenario generation
    Patent number: 7975248
    Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: July 5, 2011
    Assignee: LSI Corporation
    Inventors: Sidhesh Patel, Prakash Bodhak
  • Staged Scenario Generation
    Publication number: 20090144679
    Abstract: A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
    Type: Application
    Filed: December 3, 2007
    Publication date: June 4, 2009
    Applicant: LSI CORPORATION
    Inventors: Sidhesh Patel, Prakash Bodhak