Patents by Inventor Sidheshkumar Ramanlal Patel

Sidheshkumar Ramanlal Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Using a first-in-first-out (FIFO) wraparound address lookup table (ALT) to manage cached data
    Patent number: 11232037
    Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 25, 2022
    Assignee: Seagate Technology LLC
    Inventors: Nitin Satishchandra Kabra, Sidheshkumar Ramanlal Patel, Sneha Kishor Wagh
  • Using a First-In-First-Out (FIFO) Wraparound Address Lookup Table (ALT) to Manage Cached Data
    Publication number: 20190121740
    Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 25, 2019
    Inventors: Nitin Satishchandra Kabra, Sidheshkumar Ramanlal Patel, Sneha Kishor Wagh