Abstract: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

Abstract: A method and apparatus is provided for analyzing performance of a computer or data processing system, during the time that a specified task is running on the system. The analysis is used to furnish a system user with a list of proposed hardware component upgrades that would improve system performance in various respects, each being accompanied by a parameter value indicating the improvement a particular upgrade would provide. Usefully, listed upgrades are made available over the Internet, for purchase by system users. In an embodiment directed to a method, for use with a computer system comprising a configuration of hardware components, selected hardware components are monitored as the system performs a specified task. This is done to acquire statistics representing the operation of respective selected components. The statistics are processed, to identify at least one selected component that impedes the system in performing the task.

Abstract: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

Abstract: A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger thread is functioning, the debugger thread invokes an operational thread. In turn, the operational thread loads a primary operating system and may run various applications. While the operational thread executes the primary operating system and the applications, the debugger thread monitors the operational thread for proper functionality. When the operational thread crashes or terminates, the debugger thread retrieves operational data from the operational thread and provides the operational data to a software developer for analysis.