Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface includes the formation of a blind hole from the back side surface, forming a passivating layer therein, removing passivation material from the blind hole bottom, depositing at least one conductive layer within the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material.

Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: Methods for forming blind wafer interconnects (BWIs) from the back side of a previously thinned substrate structure such as a semiconductor wafer to the underside of a bond pad on its active surface includes the formation of a blind hole from the back side, application of a passivating layer therein, anisotropically etching to remove passivation material from the blind hole bottom, blanket-depositing at least one conductive layer within the blind hole and over the back side, blanket-depositing a resist in the blind hole and over the back side, planarizing the back side to remove resist and the at least one conductive layer, removing resist from the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material.

Abstract: Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Abstract: Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a microelectronic die, an image sensor, and an integrated circuit operatively coupled to the integrated circuit. The microelectronic imager also includes an optic unit having an optic member. The microelectronic imager further includes a prefabricated housing having a first mounting site and a second mounting site. The die is seated within the housing at the first mounting site and the optics unit is seated within the housing at the second mounting site in a fixed, preset position in which the optic member is situated at a desired location relative to the image sensor.

Abstract: Methods for forming interconnects in blind holes and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having microelectronic dies with integrated circuits and terminals electrically coupled to the integrated circuits. In one embodiment, the method includes forming a blind hole in the workpiece. The blind hole extends from a first exterior side of the workpiece to an intermediate depth in the workpiece. The method continues by forming a vent in the workpiece. The vent is in fluid communication with the blind hole. The method further includes constructing an electrically conductive interconnect in at least a portion of the blind hole.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: Materials for use in programmed material consolidation processes, such as stereolithography, include a selectively consolidatable material and a filler. The filler may be included to optimize one or more physical properties of the material. The material is both selectively consolidatable and includes the desired physical property. Examples of physical properties that may optimized in a selectively consolidatable compound by mixing a filler material with a selectively consolidatable material include, without limitation, coefficient of thermal expansion, rigidity, fracture toughness, thermal stability, and strength.

Abstract: A fabrication substrate for use in fabricating integrated circuits and other electronic devices includes a substrate that comprises semiconductor material, as well as a support structure on an active surface of the substrate. The support structure is located at or adjacent to an entire outer peripheral edge of the substrate. The support structure may be configured as a ring-like element or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.