Abstract: A sensor arrangement according to an embodiment includes a substrate, and at least one sensor and a control circuit mounted on the substrate, wherein the at least one sensor and the control circuit are located on the substrate to be mountable inside a battery cell and outside the battery cell, respectively.

Abstract: A sensor arrangement according to an embodiment includes a substrate, and at least one sensor and a control circuit mounted on the substrate, wherein the at least one sensor and the control circuit are located on the substrate to be mountable inside a battery cell and outside the battery cell, respectively.

Abstract: In the present method for use in verification of a device, a plurality of injection flags are provided, each of which is associated with one of a plurality of packet classes. Each injection flag may be of a first or a second state. Next, a packet is generated. If the injection flag of the packet class of the generated packet is in the second state, it is indicated that a packet of that packet class has already been generated, and the device is not tested. If the injection flag of the packet class of the generated packet is in the first state, the device is tested and the injection flag of the packet class of the generated packet is set to the second state. The process is repeated, the running of subsequent tests being determined by the state of the injection flag of the packet class of the generated packet.

Abstract: A method and arrangement for testing different types of external memories that can be coupled to a network interface controller. The network interface controller interprets the results of the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.

Abstract: A method and arrangement for performing a memory built-in self test (MBIST) of an external memory and an internal memory of a network interface controller includes a series of burst write and burst read operations if an external memory is detected. The sequence of burst operations tests the back-to-back burst write, back-to-back burst write burst read, back-to-back burst read and back-to-back burst read burst write capabilities of the external memory, to thereby fully exercise the external memory. Additionally, the internal memory is tested by single write and single read accesses.