Patents by Inventor Sie Wei Henry Lau

Sie Wei Henry Lau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory access bases on erase cycle time
    Patent number: 9588695
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Mee-Choo Ong, Wei-Kent Ong, Ogiwara Yuusuke, Sie-Wei Henry Lau
  • Memory Access Bases on Erase Cycle Time
    Publication number: 20150253988
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: Spansion LLC
    Inventors: Mee-Choo ONG, Wei-Kent ONG, Ogiwara YUUSUKE, Sie-Wei Henry LAU
  • For test (DFT) read speed through transition detector in built-in self-test (BIST) sort
    Patent number: 8964484
    Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Spansion LLC
    Inventors: Mee-Choo Ong, Sheau-Yang Ch'ng, Boon-Weng Teoh, Sie Wei Henry Lau, Jih Hong Beh, Wei-Kent Ong
  • DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT
    Publication number: 20140185393
    Abstract: A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Spansion, LLC.
    Inventors: Mee-Choo ONG, Sheau-Yang Ch'ng, Boon-Weng Teoh, Sie Wei Henry Lau, Jih Hong Beh, Wei-Kent Ong