Abstract: The network comprises at least one network layer in which a plurality of electronic oscillators, interconnected via programmable coupling elements storing respective network weights, generate oscillatory signals at time delays dependent on the input signal to propagate the input signal from an input to an output of that layer. The network is adapted to provide a network output signal dependent substantially linearly on phase of oscillatory signals in the last layer of the network. The method includes calculating a network error dependent on the output signal and a desired output for the training sample, and calculating updates for respective network weights by backpropagation of the error such that weight-updates for a network layer are dependent on a vector of time delays at the input to that layer and the calculated error at the output of that layer.

Abstract: A network comprises a plurality of oscillators. The network is configured to control the phase of the plurality of oscillators by thermal coupling through a thermal link.

Abstract: A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.

Abstract: A device includes at least one tunable resistive element. Each tunable resistive element comprises a first terminal, a second terminal, and a dielectric layer arranged between the first and second terminals. The device is configured to apply at least one electrical set pulse to the resistive elements to form a conductive filament comprising a plurality of oxygen vacancies in the dielectric layer. The device is configured to apply at least one electrical reset pulse to displace a subset of the oxygen vacancies of the conductive filament. The at least one electrical reset pulse comprises a first part, which is adapted to increase the temperature of the conductive filament and increase the mobility of the oxygen vacancies of the conductive filament, and a second part, which is configured to displace the subset of the oxygen vacancies of the conductive filament.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: The network comprises at least one network layer in which a plurality of electronic oscillators, interconnected via programmable coupling elements storing respective network weights, generate oscillatory signals at time delays dependent on the input signal to propagate the input signal from an input to an output of that layer. The network is adapted to provide a network output signal dependent substantially linearly on phase of oscillatory signals in the last layer of the network. The method includes calculating a network error dependent on the output signal and a desired output for the training sample, and calculating updates for respective network weights by backpropagation of the error such that weight-updates for a network layer are dependent on a vector of time delays at the input to that layer and the calculated error at the output of that layer.

Abstract: An electronic circuit for enabling an efficient use of an oscillating neural network for feature recognition may be provided. The electronic circuit comprises a network of coupled voltage-controlled oscillators, wherein each of the voltage-controlled oscillators is adapted for receiving an edge input signal which is phase-shifted by a fraction of a period length of the voltage-controlled oscillators according to a signal strength of an analog input signal allotted to a respective one of the voltage-controlled oscillators, and an active output circuit. The active output circuit includes input terminals connected to selected ones of the voltage-controlled oscillators, an adder portion for adding input signals present at the input terminals, and a non-linear amplifier, an which input line is of the non-linear amplifier being connected to an output line of the adder portion, thereby an efficient use of an oscillating neural network.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction.

Abstract: A complementary logic element including first and second transistor elements. The first and second gate electrodes of the two transistor elements are electrically parallel to form a common gate. Both the coupling layers of the first and the second transistor element include a resistance switching material, a conductivity of which may be altered by causing an ion concentration to alter if an electrical voltage signal of an appropriate polarity is applied. The first and second transistor elements also include an ion conductor layer that is capable of accepting ions from the coupling layer and of releasing ions into the coupling layer. The coupling layers and ion conductor layers are such that the application of an electrical signal of a given polarity to the gate enhances the electrical conductivity of the first coupling layer and diminishes the electrical conductivity of the second, or vice versa.

Abstract: In accordance with an aspect of the present disclosure, a memory cell (1) or select element is provided. The element includes an ion conductor element (3) formed of a ion conductor material with mobile metal ions, a first electrically conducing electrode (4) in electrical contact with the ion conductor element, and a second electrically conducting electrode (6) in electrical contact with the ion conductor element, so that the memory cell or select element is programmable by applying an electrical voltage between the first electrode and the second electrode that causes the metal ions to be influenced so that an electrical resistance across the ion conductor element is caused to vary, for example because a metallic protrusion (7) is caused to grow or decompose. In contrast to prior art approaches, the ion conductor element has a shape that is asymmetrical with respect to an exchange of the first electrode (4) and the second electrode (6) for each other.

Abstract: A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode.

Abstract: A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode.

Abstract: A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode.

Abstract: In accordance with an aspect of the present disclosure, a memory cell (1) or select element is provided. The element includes an ion conductor element (3) formed of a ion conductor material with mobile metal ions, a first electrically conducing electrode (4) in electrical contact with the ion conductor element, and a second electrically conducting electrode (6) in electrical contact with the ion conductor element, so that the memory cell or select element is programmable by applying an electrical voltage between the first electrode and the second electrode that causes the metal ions to be influenced so that an electrical resistance across the ion conductor element is caused to vary, for example because a metallic protrusion (7) is caused to grow or decompose. In contrast to prior art approaches, the ion conductor element has a shape that is asymmetrical with respect to an exchange of the first electrode (4) and the second electrode (6) for each other.

Abstract: A programmable magnetoresistive memory cell. The memory cell has a magnetic element that includes a first and a second ferromagnetic layer. The first and second ferromagnetic layers are separated by a non-ferromagnetic and preferably electrically insulating spacer layer. The data bit is read out by measuring the electrical resistance across the magnetic element. The memory cell further includes: a third ferromagnetic layer having a well-defined magnetization direction and a resistance switching material having a carrier density. The carrier density can be altered by causing an ion concentration to become altered by means of an applied electrical voltage signal. Thus, the carrier density can be switched between a first and second state.

Abstract: A programmable device including a source-drain-gate structure. The device includes two programming electrodes and an antiferromagnetic multiferroic material between the two programming electrodes for switching the spontaneous polarization between a first spontaneous polarization direction and a second spontaneous polarization direction. The programmable device further includes a ferromagnetic material, which is in immediate contact with the multiferroic material. Magnetization of the ferromagnetic material is switchable by a transition between the first switching state and the second switching state of the multiferroic material by an exchange coupling between electronic states of the multiferroic material and the ferromagnetic material. The programmable device also includes means for determining a direction of the magnetization of the ferromagnetic material. A spin valve effect is used for causing an electrical resistance between the source and the drain electrode.

Abstract: A programmable magnetoresistive memory cell. The memory cell has a magnetic element that includes a first and a second ferromagnetic layer. The first and second ferromagnetic layers are separated by a non-ferromagnetic and preferably electrically insulating spacer layer. The data bit is read out by measuring the electrical resistance across the magnetic element. The memory cell further includes: a third ferromagnetic layer having a well-defined magnetization direction and a resistance switching material having a carrier density. The carrier density can be altered by causing an ion concentration to become altered by means of an applied electrical voltage signal. Thus, the carrier density can be switched between a first and second state.

Abstract: A complementary logic element including first and second transistor elements. The first and second gate electrodes of the two transistor elements are electrically parallel to form a common gate. Both the coupling layers of the first and the second transistor element include a resistance switching material, a conductivity of which may be altered by causing an ion concentration to alter if an electrical voltage signal of an appropriate polarity is applied. The first and second transistor elements also include an ion conductor layer that is capable of accepting ions from the coupling layer and of releasing ions into the coupling layer. The coupling layers and ion conductor layers are such that the application of an electrical signal of a given polarity to the gate enhances the electrical conductivity of the first coupling layer and diminishes the electrical conductivity of the second, or vice versa.