Abstract: A radially inwardly open raceway formed in a nut centered on a nut axis is machined by of oscillating the nut about the nut axis while pressing a tool secured in a holder radially outwardly into the raceway of the nut. The holder is moved parallel to the nut axis and oscillated about a tool axis perpendicular to the nut axis synchronously with the oscillation of the nut about the nut axis. Springs brace the tool against the holder parallel to the nut axis such that the tool can move limitedly in the holder against spring bias parallel to the tool axis.

Abstract: A radially inwardly open raceway formed in a nut centered on a nut axis is machined by of oscillating the nut about the nut axis while pressing a tool secured in a holder radially outwardly into the raceway of the nut. The holder is moved parallel to the nut axis and oscillated about a tool axis perpendicular to the nut axis synchronously with the oscillation of the nut about the nut axis. Springs brace the tool against the holder parallel to the nut axis such that the tool can move limitedly in the holder against spring bias parallel to the tool axis.

Abstract: An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.