Abstract: Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.

Abstract: Failure and repair information collected during self-testing of arrays in an integrated circuit is stored in a centralized array in the integrated circuit. In that way, a centralized array can be read out to provide failure and repair information on the arrays in the integrated circuit rather than having to read from each array. In addition, the failure and repair information may also be stored in the array under test for certain of the arrays.

Abstract: An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.

Abstract: An extended host controller test mode support is provided. In the example of USB host controllers, an enhanced host controller is provided to control the high-speed traffic. Further at least one companion host controller controls the full-speed and/or low-speed traffic. The enhanced host controller comprises a test circuit for controlling a USB transceiver macrocell to perform full-speed and/or low-speed test functions. The test functions may include a test-J function, a test-K function, a single-ended-zero test function, and the sending of test patterns.

Abstract: A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Abstract: A diagnosis mechanism for host controllers such as USB (Universal Serial Bus) host controllers is provided. The host controller has a register set that comprises at least one host controller capability register storing data indicative of operational capabilities of the host controller, and at least one host controller operational register storing data for controlling the operation of the host controller. The at least one host controller capability register stores data that is indicative of available diagnostic modes that the host controller can enter. The at least one host controller operational register stores diagnosis data for controlling the operation of the USB host controller in diagnostic modes. This diagnosis mechanism may improve the reliability of the host controller operation.

Abstract: A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

Abstract: A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.

Abstract: A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.

Abstract: A method of manufacturing a metal layer structure and a corresponding integrated circuit chip are provided, wherein the integrated circuit chip comprises metal layers and via holes. The via holes electrically connect a metal line of one metal layer with a metal line of another metal layer. The metal lines and via holes form a signal path that electrically connects a first tap with a second tap. The metal lines in each metal layer are arranged in a first predefined configuration. There is for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with a third tap. This technique is particularly useful for storing revision identification data.

Abstract: A method of manufacturing a metal layer structure and a corresponding integrated circuit chip are provided, wherein the integrated circuit chip comprises metal layers and via holes. The via holes electrically connect a metal line of one metal layer with a metal line of another metal layer. The metal lines and via holes form a signal path that electrically connects a first tap with a second tap. The metal lines in each metal layer are arranged in a first predefined configuration. There is for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with a third tap. This technique is particularly useful for storing revision identification data.

Abstract: An extended host controller test mode support is provided. In the example of USB host controllers, an enhanced host controller is provided to control the high-speed traffic. Further at least one companion host controller controls the full-speed and/or low-speed traffic. The enhanced host controller comprises a test circuit for controlling a USB transceiver macrocell to perform full-speed and/or low-speed test functions. The test functions may include a test-J function, a test-K function, a single-ended-zero test function, and the sending of test patterns.

Abstract: A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Abstract: A USB (Universal Serial Bus) host controller, a corresponding integrated circuit chip, a computer system and an operation method are provided for handling the data traffic between at least one USB device and the computer system having system memory. A transaction processing unit processes transactions to or from the at least one USB device. Further, a transaction duration management unit is provided for determining estimated duration values of the transactions. The transaction processing unit is adapted to process the transactions dependent on the estimated duration values. A descriptor-to-transaction converter may be provided, and the prefetched mechanism may be made dependent on a threshold value relating to the estimated duration values.

Abstract: A data storage mechanism is provided where a plurality of data items are stored in a plurality of register elements. Each registered element is capable of storing at least one data item. The plurality of register elements is arranged to form a sequence of register elements. First data is stored in a first part of the sequence and second data is stored in a second part of the sequence. The first part and the second part are of variable lengths with the sum of the variable lengths being equal to the lengths of the sequence of register elements. Thus, a double-ended queue mechanism is provided which may be used to store data of different type or data which is either scheduled periodically or asynchronously. The mechanism may be used in a USB 2.0 compliant host controller.

Abstract: A USB host controller is provided for handling the data traffic between at least one USB device and a system memory of a computer system. The USB host controller comprises a data fetch unit for fetching data elements from the system memory, a storage unit for storing the fetched data elements, and a transaction processing unit for processing transactions sent to or received from the USB device dependent on the fetched data elements stored in the storage unit. The data fetch unit and the transaction processing unit are arranged for operating asynchronously. The host controller may be USB 2.0 compliant and may be realized in a southbridge.

Abstract: A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.