Abstract: A circuit configuration for generating an enable signal for a clock-controlled circuit includes a device for generating a power-on reset signal. Deactivation of that signal is delayed through the use of a delay device, and is used for enabling a clock signal output by an oscillator. The circuit is controlled in clocked fashion through the use of the signal. A delay time of the delay device is controlled by the oscillator through a level weighting device, preferably a Schmitt trigger. As a result, the clock signal is not enabled until the oscillator is oscillating at stable amplitude and at a desired frequency.