Abstract: A circuit arrangement for supplying interrupt requests signals from a peripheral unit to a central processing unit of a computer system over a common control line, without a priority scheme. A blocking circuit is provided such that the first interrupt signal on the common control line blocks any further interrupt signals on that line until the interrupt has been processed. Since no further interrupts are possible, the interrupt acknowledged signal from the central processing unit need not contain the address of the external unit having requested the interrupt nor need there be provided a circuit to process the interrupt acknowledge signal in the peripheral unit. An interrupt signal present on the common interrupt line blocks generation of subsequent interrupt signals from reaching the common interrupt line by a combination of the two interrupting switches together with a delay after the first switch.