Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.

Abstract: The invention relates to a detection procedure for bacteria of the genus Listeria, comprising the steps:(a) provision of a DNA vector prepared by means of recombination techniques, comprising a genetic system comprising DNA which encodes the expression of one or more proteins, the proteins not being a gene product of bacteria of the genus Listeria and it being possible to determine the presence of the proteins by a detection reaction, and the DNA vector infecting the bacteria of the genus Listeria and it being possible in this way to transfer the genetic system to the bacteria;(b) mixing of the sample with said DNA vector under conditions which allow an infection of bacteria of the genus Listeria by the DNA vector;(c) expression of the detectable proteins in the bacteria of the genus Listeria;(d) detection of the detectable proteins, the presence of bacteria of the genus Listeria being detected,and to recombinant DNA vectors and reagent compositions suitable for this detection procedure.