Abstract: A circuit for matching sense amplifier trigger signal timing to data bit line separation timing in a self-timed memory array includes: a source of a self-timed word line signal for a self-timed memory array; a transmission gate coupled to the source of the self-timed word line signal for propagating a timing delay and a ramp rate of the self-timed word line signal in response to a corresponding self-timed word line enable signal; and a selectable number of one or more self-timed pull-down core cells for summing a self-timed bit line drive current of each of the selectable number of one or more self-timed pull-down core cells to generate a sense amplifier trigger signal.

Abstract: A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.

Abstract: A memory having built-in self repair with row shifting is provided. The rows in the memory are divided into smaller row groups and a bad row group is repaired with a redundant row group. Each row group receives a row select signal, which is fed into a shift circuit for the row group and a shift circuit for an adjacent row group. A shift circuit is provided for the redundant row group and the shift circuit for the redundant row group receives the row select signal for only the adjacent row group. If a bad row group is detected, then starting with the row group furthest from the redundant row group, the shift circuit for each row group before the bad row group is deactivated. The row group select signal and word line signal for the bad row group are disabled. The shift circuit for the bad row group and the shift circuit for each row group after the bad row group are activated. Therefore, the bad row group is disabled and the redundant row group fills the void.

Abstract: A memory having built-in self repair with column shifting is provided. The total single columns are divided into smaller column groups and a bad column group is repaired with a redundant column group. Each column group is multiplexed into a pair of column group bitlines, which are fed into a shift circuit for the column group and a shift circuit for an adjacent column group. The shift circuit for the column group nearest the redundant column group receives the bitlines for that column group and the redundant column group bitlines. If a bad column group is detected, then starting with the column group furthest from the redundant column group, the shift circuit for each column group before the bad column group is deactivated. The shift circuit for the bad column group and the shift circuit for each column group after the bad column group are activated. Therefore, the bad column group is shifted out of the memory and the redundant column group fills the void.

Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

Abstract: A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.