Abstract: Disclosed is a pictorial image compression device comprising an A/D converter converting an analog image input signal into digital image data, a clock dropout circuit producing a dropout indication signal and a partly dropped-out clock on the basis of a write clock and data of a selected compression rate, an averaging circuit averaging the image data according to the partly dropped-out write clock, a memory successively storing the image output data from the averaging circuit in response to the partly dropped-out write clock, a reading circuit reading out the image data stored in the memory, and a D/A converter converting the image data read out by the reading circuit into an analog signal, so that images can be continuously compressed without highlighting undesirable discontinuity at the edge of each image. Thus, the device can continuously compress image data in spite of its simple circuit structure.

Abstract: A horizontal synchronizing signal separator in accordance with the present invention comprises an activation signal generator, when subjected to a triggering operation, for generating an activation signal having a predetermined continuous ON time duration, a front edge detector for outputting either one of first and second start pulses according to states of a video synchronizing pulse signal and the activation signal, and a first timer for making timing of the activation signal substantially coincide with timing of a front edge of the video synchronizing pulse signal on the basis of a composite signal corresponding to a composition of the first and second output signals, whereby, even in the case of a missing pulse or pulses in the video synchronizing pulse signal, the missing pulses are corrected with less phase shift in horizontal synchronization.

Abstract: In a device for producing a composite video picture display by combining digital video signals, a soft wipe signal is produced with an inclination from an input wipe signal, delayed pulses are produced by delay circuits for vertical-wise delays in the picture display and by shift registers for horizontalwise delays in the picture, and digital values of these pulses are normalized by an adder and a multiplier to produce the soft wipe signal.

Abstract: A digital wipe pattern generating device includes address generators for counting horizontal and vertical synchronization pulses to generate addresses; a calculator for obtaining wipe address data by effecting a plurality of sorts of calculations in a digital manner while using predetermined coefficients, combining and selecting arbitrarily results of the calculations; and a device for generating a wipe pattern by slicing the wipe address data at a predetermined slice level. Since all processings are effected in a digital manner, it is easier to fabricate the device, using ASICs or ICs, and thus the scale of the circuits can be reduced.

Abstract: In accordance with the present invention, a vertical synchronizing pulse is compared with output of a field decision circuit by using a frequency division circuit for exercising frequency division with a ratio of 1/2. Even if an error is caused in the field decision circuit, therefore, a field pulse every vertical synchronizing can be outputted accurately.