Abstract: An FS signal demodulator includes a zero-crossing detector which detects zero-crossings of frequency shift signals (FS), a pulse converter which generates a train of "0" and "1", "0" representative of a time slot from the first detected zero-crossing through a given period of time and "1" representative of a time slot from that period through the next succeeding zero-crossing, a memory means receiving the outputs of the pulse converter and thus containing the train of the pulses with the length corresponding to modulation rate, a counter means counting the number of "1's" or "0's" contained within the memory means in response to clock signals, and a determination circuit which effects frequency discrimination by comparing the counts of the counter means with a given limit.