Abstract: A data transfer apparatus transfers data between a source and a destination on a clock having a phase with a signal delay over a connection line taken into account to allow a plurality of destinations to capture the transfer data on the same clock timing. Optimized data transfer and high-speed data transfer are thus realized, which in turn significantly enhances the performance of the data transfer apparatus.

Abstract: An apparatus for controlling a data transfer between storages in an information processing system having a main storage, an extended storage, and a processor in which data is transferred between the main storage and the extended storage by use of a synchronous instruction and an asynchronous instruction. The apparatus includes a unit to hold data transfer control information specified by the asynchronous instruction and a unit to hold data transfer control information specified by the synchronous instruction. Depending on a synchronous instruction or an asynchronous instruction, the data transfer is controlled to be achieved according to data transfer control information held in the unit associated with the instruction. The content of the unit is updated depending on the amount of data to be transferred.