Patents by Inventor Sigeru Kuriyama

Sigeru Kuriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6552551
    Abstract: In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 22, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michio Komoda, Sigeru Kuriyama
  • Publication number: 20020036508
    Abstract: In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.
    Type: Application
    Filed: June 12, 2001
    Publication date: March 28, 2002
    Inventors: Michio Komoda, Sigeru Kuriyama
  • Patent number: 4124088
    Abstract: A velocity at the time when the accelerator of a vehicle is released is stored under a certain condition in advance, and the stored vehicle velocity and an actual vehicle velocity are compared. When the actual vehicle velocity becomes greater than the stored vehicle velocity by a predetermined value, the downward inclination of a running road surface is regarded as exceeding a predetermined value, and safety means such as a brake is driven. As compared with a case of employing an inclination angle sensor such as a mercury switch, the device operates accurately without being influenced by a change in the vibration or acceleration of the vehicle.
    Type: Grant
    Filed: August 12, 1976
    Date of Patent: November 7, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Sigeru Kuriyama, Minoru Kaminaga
  • Patent number: 4079270
    Abstract: In a semiconductor device which includes a main thyristor and an auxiliary thyristor for turning off the main thyristor and controls conduction period of the main thyristor according to a given duty factor, a gate control apparatus comprising a phase shifter for producing a square wave output corresponding to the duty factor, an integrator for integrating the output of the phase shifter, a relay circuit having two level settings and receiving the output from the integrator to produce an output which exhibits a hysterisis characteristic corresponding to the two level settings, and an amplifier for turning on the main thyristor in response to the output from the relay circuit and turning on the auxiliary thyristor upon the termination of the output from the relay circuit.
    Type: Grant
    Filed: April 28, 1976
    Date of Patent: March 14, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Ibamoto, Masato Suzuki, Sigeru Kuriyama