Patents by Inventor Sigeru Nose

Sigeru Nose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data delay/memory circuit
    Patent number: 4802136
    Abstract: A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock signals have individual clocking phases and are sequentially generated such that the clocking phase for a final stage of the data latch circuits is ahead of that for an initial stage thereof.
    Type: Grant
    Filed: April 29, 1988
    Date of Patent: January 31, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sigeru Nose, Seigo Suzuki