Abstract: The display device includes data lines, first gate lines arranged in parallel with the data lines, second gate lines intersecting the first gate lines, a line contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are in contact with each other, a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other in an intersection area thereof, a first pixel including a first switching element connected to a corresponding second gate line among the second gate lines, and a second pixel including a second switching element connected to the second gate line connected to the first pixel, wherein magnitude of a first capacitance of the first switching element is different from magnitude of a first capacitance of the second switching element.

Abstract: A display device includes a first conductive layer including horizontal scan lines, and island-type electrodes, which are spaced apart from the horizontal scan lines; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including data lines, and a plurality of vertical scan lines; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including first shield electrodes, which cover first edges of the vertical scan lines, and second shield electrodes, which are spaced apart from the first shield electrodes, and cover second edges of the vertical scan lines, wherein the vertical scan lines are electrically connected to the island-type electrodes via contact holes that extend through the first insulating layer.

Abstract: A display device includes a first conductive layer including horizontal scan lines, and island-type electrodes, which are spaced apart from the horizontal scan lines; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including data lines, and a plurality of vertical scan lines; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including first shield electrodes, which cover first edges of the vertical scan lines, and second shield electrodes, which are spaced apart from the first shield electrodes, and cover second edges of the vertical scan lines, wherein the vertical scan lines are electrically connected to the island-type electrodes via contact holes that extend through the first insulating layer.

Abstract: A display device includes a first conductive layer including horizontal scan lines, and island-type electrodes, which are spaced apart from the horizontal scan lines; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including data lines, and a plurality of vertical scan lines; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including first shield electrodes, which cover first edges of the vertical scan lines, and second shield electrodes, which are spaced apart from the first shield electrodes, and cover second edges of the vertical scan lines, wherein the vertical scan lines are electrically connected to the island-type electrodes via contact holes that extend through the first insulating layer.

Abstract: A display device includes a first conductive layer including horizontal scan lines, and island-type electrodes, which are spaced apart from the horizontal scan lines; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer, the second conductive layer including data lines, and a plurality of vertical scan lines; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer and including first shield electrodes, which cover first edges of the vertical scan lines, and second shield electrodes, which are spaced apart from the first shield electrodes, and cover second edges of the vertical scan lines, wherein the vertical scan lines are electrically connected to the island-type electrodes via contact holes that extend through the first insulating layer.

Abstract: The display device includes data lines, first gate lines arranged in parallel with the data lines, second gate lines intersecting the first gate lines, a line contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are in contact with each other, a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other in an intersection area thereof, a first pixel including a first switching element connected to a corresponding second gate line among the second gate lines, and a second pixel including a second switching element connected to the second gate line connected to the first pixel, wherein magnitude of a first capacitance of the first switching element is different from magnitude of a first capacitance of the second switching element.

Abstract: A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.

Abstract: A thin film transistor array panel includes a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate where a constant voltage is applied thereto; a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor.

Abstract: A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value.

Abstract: A display device includes a plurality of gate lines arranged substantially parallel to each other in a first direction; a plurality of charge share gate lines arranged substantially parallel to each other in the first direction; a plurality of data lines arranged substantially parallel to each other in a second direction, wherein the second direction is substantially perpendicular to the first direction; and a plurality of pixels arranged in a matrix form in along the first direction and the second direction and each of the plurality of pixels which includes a first switching element and a second switching element, wherein the a first gate line of the plurality of gate lines is electrically connected to the first switching element included in one individual pixel of the plurality of pixels, and the a second gate line of the plurality of gate lines is electrically connected to the second switching element included in the individual pixel of the plurality of pixels.

Abstract: Provided is a gate driving circuit including cascade-connected stages that output gate signals. An n-th one of the stages (“n” is a natural number) includes a pull-up part, a pull-up controller, a first pull-down part, a second pull-down part, and a pull-down controller. The pull-up part outputs a first clock signal as an output signal of the n-th stage. The pull-up controller selectively applies first and second powers to a control electrode of the pull-up part. The first pull-down part pulls down a voltage applied to the control electrode of the pull-up part to an off voltage. The second pull-down part pulls down a voltage applied to an output electrode of the pull-up part to the off voltage. The pull-down controller selectively applies the first and second powers to control electrodes of the first and second pull-down parts.

Abstract: A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode; and a gate insulating layer disposed between the gate electrode and the source electrode or between the gate electrode and the drain electrode, wherein when a signal applied to the gate electrode is a turnoff signal, a voltage applied to the gate electrode has a negative value.

Abstract: A thin film transistor array panel includes a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate where a constant voltage is applied thereto; a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor.

Abstract: A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.

Abstract: A display apparatus includes first, second, and third gate driving chips applying gate signals to gate lines. A gate driving voltage is applied to the first gate driving chip and a gate driving voltage of the same level is applied to the second and third gate driving chips. In addition, the display apparatus includes a plurality of photo-sensors and first, second, and third scan driving chips applying scan signals to scan lines connected to the photo-sensors. A scan driving voltage is applied to the first scan driving chip and a scan driving voltage of the same level is applied to the second and third scan driving chips.

Abstract: A thin film transistor array panel includes a first substrate; a gate line and a data line on the first substrate; a storage electrode line on the first substrate where a constant voltage is applied thereto; a first thin film transistor and a second thin film transistor which are connected to the gate line and the data line; a third thin film transistor which is connected to the gate line, the second thin film transistor and the storage electrode line; a first subpixel electrode which is connected to the first thin film transistor; and a second subpixel electrode which is connected to the second thin film transistor.

Abstract: Provided are a gate driving apparatus and a display device including the same. The gate driving apparatus includes a plurality of stages arranged sequentially, each stage is adapted to output a gate signal and including first output lines and a second output line, wherein the first output lines are electrically connected to a gate line corresponding to each of the stages and are adapted to transmit the gate signal to a plurality of pixels coupled to the gate line, the second output line is adapted to transmit the gate signal to a preceding stage of each of the stages, and the first output lines and the second output line share one contact pad.

Abstract: A liquid crystal display includes a first gate line; a common voltage line separated from the first gate line; a data line insulated from and crossing the first gate line and the common voltage line; a first switching element connected to the first gate line and the data line; a second switching element connected to the first gate line and the data line; a first liquid crystal capacitor connected to the first switching element; a second liquid crystal capacitor connected to the second switching element; a third switching element connected to the first switching element; an assistance capacitor connected to the third switching element and the common voltage line; and a shielding electrode extending in the same direction as the first gate line and connected to the first switching element.

Abstract: The present invention relates to a thin film transistor array panel including: a substrate; gate lines formed on the substrate; and a gate driver formed on the substrate to apply gate signals to the gate lines. The gate driver includes a first wire and a second wire to transmit different signals, and at least one of the first wire and the second wire includes a static electricity preventing structure to prevent static electricity from accumulating between the first wire and the second wire.

Abstract: A liquid crystal display, the liquid crystal display comprises a plurality of gate lines which includes a first gate line, a transformation gate line, and a second gate line; a data line; and a pixel, wherein the pixel includes a first liquid crystal capacitor which includes a first sub-pixel electrode and a common electrode and a second liquid crystal capacitor which includes a second sub-pixel electrode and a common electrode; a first switching element connected to the first gate line, the data line, and the first sub-pixel electrode; a second switching element connected to the first gate line, the data line, and the second sub-pixel electrode; a third switching element connected to the transformation gate line and the second switching element; a transformation capacitor which includes a first terminal connected to the second gate line and a second terminal connected to the third switching element; and a first period where a gate-on voltage Von is applied to the first gate line and a second period where the