Patents by Inventor Sik K. Lui

Sik K. Lui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418899
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change. The first MOS transistor has a first threshold voltage and the second MOS transistor has a second threshold voltage where the first threshold voltage is less than the second threshold voltage.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 17, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Daniel S. Ng, Xiaobin Wang
  • Patent number: 10032584
    Abstract: This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 24, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Anup Bhalla
  • Publication number: 20180138906
    Abstract: This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.
    Type: Application
    Filed: December 30, 2014
    Publication date: May 17, 2018
    Inventors: Sik K. Lui, Anup Bhalla
  • Patent number: 9806175
    Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: October 31, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Daniel Ng., Tiesheng Li, Sik K. Lui
  • Publication number: 20170288034
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: April 27, 2017
    Publication date: October 5, 2017
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Patent number: 9741851
    Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 22, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K Lui, Anup Bhalla
  • Patent number: 9716156
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: May 2, 2015
    Date of Patent: July 25, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Publication number: 20160322469
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: May 2, 2015
    Publication date: November 3, 2016
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • Publication number: 20160247899
    Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.
    Type: Application
    Filed: February 23, 2015
    Publication date: August 25, 2016
    Inventors: Anup Bhalla, Daniel Ng, Tiesheng Li, Sik K. Lui
  • Publication number: 20160191048
    Abstract: This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 30, 2016
    Inventors: Sik K. Lui, Anup Bhalla
  • Publication number: 20150295495
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal. The first and second MOS transistors have respective gate terminals coupled to the control terminal to receive a control signal to turn the switch circuit on or off where the control signal transitions from a first voltage level to a second voltage level at a slow rate of change.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Daniel S. Ng, Xiaobin Wang
  • Publication number: 20150206943
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Inventors: Madhur Bobde, Sik K. Lui, Anup Bhalla
  • Patent number: 9024378
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: May 5, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Patent number: 9013848
    Abstract: A protection circuit for a power transistor includes a first transistor connected in parallel with the power transistor and having a control terminal connected to a first power supply voltage through a first resistive element; and a first set of diodes connected between a first terminal and a control terminal of the first transistor. In operation, the voltage at the first terminal of the first transistor is clamped to a clamp voltage and the first transistor is turned on to conduct current in a forward conduction mode when an over-voltage condition occurs at a first terminal of the power transistor.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Sik K. Lui
  • Patent number: 8963233
    Abstract: This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Daniel Ng, Tiesheng Li, Sik K. Lui
  • Patent number: 8963240
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik K. Lui
  • Patent number: 8946942
    Abstract: This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: February 3, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik K. Lui, Anup Bhalla
  • Publication number: 20140332882
    Abstract: A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 13, 2014
    Inventors: SiK K. Lui, Anup Bhalla
  • Publication number: 20140319606
    Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Inventors: Anup Bhalla, Sik K. Lui
  • Publication number: 20140225187
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: February 9, 2013
    Publication date: August 14, 2014
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui