Patents by Inventor Sik Lui
Sik Lui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869967Abstract: An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.Type: GrantFiled: August 12, 2021Date of Patent: January 9, 2024Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventors: Sik Lui, Madhur Bobde, Lingpeng Guan, Lei Zhang
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Publication number: 20230238440Abstract: A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.Type: ApplicationFiled: January 21, 2022Publication date: July 27, 2023Inventors: Madhur Bobde, Sik Lui, Lei Zhang, Xiaobin Wang
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Publication number: 20230049581Abstract: An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Sik Lui, Madhur Bobde, Lingpeng Guan, Lei Zhang
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Patent number: 11031390Abstract: A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.Type: GrantFiled: September 4, 2019Date of Patent: June 8, 2021Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Sik Lui
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Publication number: 20200303517Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: ApplicationFiled: May 22, 2020Publication date: September 24, 2020Inventors: Yongping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
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Patent number: 10714580Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a trench contact extending to the body region formed in a contact trench. A contact implant of the second conductivity type is formed surrounding a bottom portion of the contact trench and it also forms surrounding sidewall portions of the contact trench where it contacts with the lightly doped source region to form a PN diode.Type: GrantFiled: February 7, 2018Date of Patent: July 14, 2020Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.Inventor: Sik Lui
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Patent number: 10686056Abstract: A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: GrantFiled: December 30, 2016Date of Patent: June 16, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yangping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
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Patent number: 10644118Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: June 14, 2017Date of Patent: May 5, 2020Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
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Patent number: 10553714Abstract: A trench MOSFET device is fabricated with body source regions that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.Type: GrantFiled: January 31, 2019Date of Patent: February 4, 2020Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Sik Lui
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Publication number: 20190393218Abstract: A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.Type: ApplicationFiled: September 4, 2019Publication date: December 26, 2019Inventor: Sik Lui
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Patent number: 10446545Abstract: A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.Type: GrantFiled: June 30, 2016Date of Patent: October 15, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Sik Lui
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Patent number: 10388781Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.Type: GrantFiled: May 20, 2016Date of Patent: August 20, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Madhur Bobde, Sik Lui, Ji Pan
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Publication number: 20190245051Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a trench contact extending to the body region formed in a contact trench. A contact implant of the second conductivity type is formed surrounding a bottom portion of the contact trench and it also forms surrounding sidewall portions of the contact trench where it contacts with the lightly doped source region to form a PN diode.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventor: Sik Lui
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Patent number: 10325908Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.Type: GrantFiled: April 26, 2017Date of Patent: June 18, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Sik Lui, Madhur Bobde, Ji Pan
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Publication number: 20190172945Abstract: A trench MOSFET device is fabricated with body source regions that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.Type: ApplicationFiled: January 31, 2019Publication date: June 6, 2019Inventor: Sik Lui
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Patent number: 10263070Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.Type: GrantFiled: June 12, 2017Date of Patent: April 16, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yi Su, Sik Lui
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Patent number: 10256236Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.Type: GrantFiled: August 2, 2018Date of Patent: April 9, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Ji Pan, Sik Lui
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Patent number: 10211333Abstract: A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.Type: GrantFiled: April 26, 2017Date of Patent: February 19, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Madhur Bobde, Sik Lui
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Patent number: 10199492Abstract: A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.Type: GrantFiled: November 30, 2016Date of Patent: February 5, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Sik Lui
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Publication number: 20180358433Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.Type: ApplicationFiled: June 12, 2017Publication date: December 13, 2018Inventors: Yi Su, Sik Lui