Patents by Inventor Sik Lui

Sik Lui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325908
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 18, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Madhur Bobde, Ji Pan
  • Publication number: 20190172945
    Abstract: A trench MOSFET device is fabricated with body source regions that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Inventor: Sik Lui
  • Patent number: 10263070
    Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: April 16, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yi Su, Sik Lui
  • Patent number: 10256236
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 9, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Ji Pan, Sik Lui
  • Patent number: 10211333
    Abstract: A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 19, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Madhur Bobde, Sik Lui
  • Patent number: 10199492
    Abstract: A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 5, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Sik Lui
  • Publication number: 20180358433
    Abstract: Aspects of the present disclosure disclose a superjunction trench MOSFET device for low voltage or medium voltage devices and a method of fabricating the same. The superjunction trench MOSFET device according to aspects of the present disclosure comprises an active cell region and a termination region disposed at an outer periphery of the active cell region. The active cell region comprises an array of device cells with the superjunction structure. The termination region may comprise a termination structure. In one embodiment, the termination structure includes guard rings in an intrinsic epitaxial layer. In one embodiment, the termination structure includes an array of floating P columns. In another embodiment, the termination structure includes an array of floating P columns and floating termination trenches.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 13, 2018
    Inventors: Yi Su, Sik Lui
  • Publication number: 20180342506
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: Ji Pan, Sik Lui
  • Publication number: 20180315846
    Abstract: A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Madhur Bobde, Sik Lui
  • Publication number: 20180315749
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising a substrate of a first conductivity type, a body region of a second conductivity type, a gate electrode formed in a gate trench extending in the body region and substrate, a lightly doped source region and a heavily doped source region formed in the body region, and a source contact extending to the body region formed in a source contact trench next to the gate trench. The lightly doped source region is extended deeper in the body region than the heavily doped source region. The lightly doped source region is adjacent to the source contact trench. A ballast resistor is formed at the lightly doped source region between the heavily doped source region and the body region and a Schottky diode is formed at a contact between the source contact and the lightly doped source region.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Inventors: Sik Lui, Madhur Bobde, Ji Pan
  • Patent number: 10103140
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 16, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Ji Pan, Sik Lui
  • Patent number: 10062685
    Abstract: Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 28, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Ji Pan
  • Patent number: 10056461
    Abstract: Aspects of the present disclosure discloses a method for fabricating a trench MOSFET device comprising simultaneously forming a narrow trench and a wide trench into a semiconductor substrate using a mask to defines the narrow trench and the wide trench, forming an insulating layer over the semiconductor substrate with a first portion that fills up the narrow trench and a second portion that partially fills the wide trench, removing the second portion from the wide trench completely and leaving the narrow trench filled with the first portion, forming a gate electrode, forming a body region in a top portion of the semiconductor substrate, forming a source region in a portion of the body region, removing the first portion of nitride from the narrow trench, and forming a contact plug by filling a second conductive material in the narrow trench.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 21, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Hong Chang
  • Publication number: 20180151720
    Abstract: A trench MOSFET device includes a body, region and source region that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Inventor: Sik Lui
  • Publication number: 20180108652
    Abstract: A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a second terminal of the switch circuit, the first and second MOS transistors having respective gate terminals coupled to the control terminal to receive a control signal to turn the first and second MOS transistors on or off. The first MOS transistor is characterized by a first reverse gate-to-drain capacitance (Crss) and the second MOS transistor is characterized by a second Crss that is greater than the first Crss.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Inventors: Ji Pan, Sik Lui
  • Publication number: 20180097078
    Abstract: Aspects of the present disclosure discloses a method for fabricating a trench MOSFET device comprising simultaneously forming a narrow trench and a wide trench into a semiconductor substrate using a mask to defines the narrow trench and the wide trench, forming an insulating layer over the semiconductor substrate with a first portion that fills up the narrow trench and a second portion that partially fills the wide trench, removing the second portion from the wide trench completely and leaving the narrow trench filled with the first portion, forming a gate electrode, forming a body region in a top portion of the semiconductor substrate, forming a source region in a portion of the body region, removing the first portion of nitride from the narrow trench, and forming a contact plug by filling a second conductive material in the narrow trench.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Sik Lui, Hong Chang
  • Patent number: 9911840
    Abstract: A transistor device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: March 6, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Sik Lui, Anup Bhalla
  • Patent number: 9876096
    Abstract: A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate . A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 ?m to 0.2 ?m.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 23, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Madhur Bobde, Sik Lui, Hamza Yilmaz, Jongoh Kim, Daniel Ng
  • Publication number: 20180006026
    Abstract: A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventor: Sik Lui
  • Publication number: 20170338337
    Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Madhur Bobde, Sik Lui, Ji Pan