Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A method for accessing a Flash memory and an associated Flash memory system are provided, where the Flash memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of sectors. The method includes: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. An associated method and an associated Flash memory system are also provided.

Abstract: The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory, a controller, and a random access memory. The flash memory comprises a plurality of blocks for data storage. The random access memory stores a read count table for recording read counts of the blocks. When the read counts of a plurality of original blocks are greater than a threshold according to the read count table, the controller obtains a plurality of spare blocks from the flash memory as mirror blocks respectively corresponding to the original blocks, and copies a portion of a plurality of data pages of the original blocks to the mirror blocks whenever the original blocks are read until all of the data pages of the original blocks have been copied to the mirror blocks.

Abstract: The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories.

Abstract: A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided.

Abstract: A memory controller is disclosed, having a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word.

Abstract: The invention provides a bandgap reference voltage generator. In one embodiment, the bandgap reference voltage generator includes a first current generator, a second current generator, and an output voltage generator. The first current generator generates a first current with a positive temperature coefficient. The second current generator generates a second current with a negative temperature coefficient. The output voltage generator generates a third current with a level equal to that of the first current, generates a fourth current with a level equal to that of the second current, adds the third current to the fourth current to obtain a combined current with a zero temperature coefficient, and generates a reference voltage according to the combined current.

Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.