Abstract: A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, a channel hole structure in the conductor/insulator stack, and a gate line slit (GLS) structure. The GLS structure includes a main section and an end section. The main section extends along a first direction and has a first width measured along a second direction that is perpendicular to the first direction. The end section has a second width measured along the second direction. The second width is larger than the first width.

Abstract: The present disclosure discloses a three-dimensional memory and a fabrication method thereof. The fabrication method comprises: forming a stack structure comprising alternately stacked dielectric layers and sacrificial layers; forming a gate line slit penetrating vertically penetrating the stack structure and extending in a first horizontal direction; and etching portions of the dielectric layers and the sacrificial layers adjacent to the gate line slit to form a plurality of recesses, wherein an aperture of each recess in a vertical direction is greater than a thickness of a corresponding sacrificial layer.