Patents by Inventor Silke Bargstadt-Franke

Silke Bargstadt-Franke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050179088
    Abstract: An electrostatic discharge (ESD) protective apparatus for a semiconductor circuit has at least one ESD protective element, which is connected between the substrate contact and a ground potential connection, and is electrically connected to the substrate contact. The ESD protective element may be in the form of an ESD protective diode or an ESD protective transistor. It is also possible to connect a resistor or an ESD protective transistor between the substrate contact and the ground potential connection as an ESD protective element, and additionally to connect an ESD protective diode or an ESD protective transistor between the substrate contact and a supply voltage potential connection.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 18, 2005
    Inventors: Ulrich Glaser, Harald Gossner, Jens Schneider, Martin Streibl, Silke Bargstadt-Franke
  • Patent number: 6930501
    Abstract: A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 16, 2005
    Assignee: Infineon Technologies AG
    Inventors: Silke Bargstädt-Franke, Kai Esmark, Harald Gossner, Philipp Riess, Wolfgang Stadler, Martin Streibl, Martin Wendel
  • Publication number: 20050003564
    Abstract: A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.
    Type: Application
    Filed: June 14, 2004
    Publication date: January 6, 2005
    Inventors: Silke Bargstadt-Franke, Kai Esmark, Harald Gossner, Philipp Riess, Wolfgang Stadler, Martin Streibl, Martin Wendel