Patents by Inventor Silnore Sabando

Silnore Sabando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818582
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove. The method can further include separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 27, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Publication number: 20200083148
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 10483192
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Publication number: 20180269138
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 9978668
    Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor device and a metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The device can also include a molding compound encapsulating at least a portion of the metal leadframe structure. At least a portion of the signal lead can be exposed outside the molding compound. The device can further include a solder plating disposed on exposed portions of the metal leadframe structure. In the device, a flank of the signal lead can have a surface area. At first portion of the surface area of the flank can be defined by the solder plating, and a second portion of the surface area of the flank can be defined by exposed metal of the metal leadframe structure. A perimeter of a surface of the exposed metal can have at least one curved edge.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: May 22, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando