Abstract: The present invention is directed to a system and method for emulating a serial small computer system interface (SAS) connection for direct attached serial advanced technology attachment (SATA) communication are disclosed. A system in accordance with the present invention includes a host controller. The host controller includes a physical interface for accepting at least one of a SAS connection or a direct attached SATA device. A common interface logic configured to receive SAS communications and SATA communications having a SAS emulated connection is included in the host controller. An emulation logic is communicatively coupled to the common interface logic. The emulation logic being configured to determine a value of a ConnectedSata signal based on the state of a SATA link state machine.

Abstract: A novel method and apparatus for encoding input data at a faster rate provides error detection, clock recovery, and reduction of spectral components near DC, and is capable of encoding data while embedding error detection information simultaneously. This encoding scheme may encode all input data in parallel while simultaneously embedding error detection information to quickly and properly encode input data.

Abstract: The present invention is a novel system and method for implementing multiple protocol definitions including multiple interconnect protocols and protocol methods. Protocol methods may include a single-thread, multi-speed interconnect protocol method and a multi-thread, single-speed interconnect protocol method with shared resources on a single die. Various aspects of serializer/deserializer, encoder/decoder, aggregator, and protocol functions may be shared among both protocol definitions to provide cost and real estate efficiency.

Abstract: A micro-code sequencer apparatus (10) and method includes a state machine controller (14) and an instruction memory (24) for executing instructions and branches. The branch conditions for each state are stored in the state machine controller (14) whereas reprogrammable calculation instructions are stored in instruction memory (24). The instruction memory (24) is accessed by a program counter (20) which receives the decoded state information to determine the location of its instruction. A processor (30) processes the instruction and sends the output to a next state decoder (32) which determines the next state based on the branch conditions.

Abstract: A micro-sequencer apparatus (10) allows a plurality of threads to independently process one or several algorithms using common components by allowing each thread to execute one instruction during a cycle. A thread counter (12) identifies the current thread to allow processing of its instruction. A thread program counter (16) stores the program count or address for the current instruction for the current thread. An instruction memory (20) stores all instructions, and the program count identifies the particular instruction for processing. A processor (26) receives input information unique to the current thread and processes same with the current instruction to produce an output.