Patents by Inventor Silvia H. Chan

Silvia H. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage
    Patent number: 10312361
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 4, 2019
    Assignee: The Regents of the University of California
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • TRENCHED VERTICAL POWER FIELD-EFFECT TRANSISTORS WITH IMPROVED ON-RESISTANCE AND BREAKDOWN VOLTAGE
    Publication number: 20170125574
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 4, 2017
    Applicants: The Regents of the University of Calfornia, Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • METALORGANIC CHEMICAL VAPOR DEPOSITION OF OXIDE DIELECTRICS ON N-POLAR III-NITRIDE SEMICONDUCTORS WITH HIGH INTERFACE QUALITY AND TUNABLE FIXED INTERFACE CHARGE
    Publication number: 20160163846
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Application
    Filed: January 28, 2016
    Publication date: June 9, 2016
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • Metalorganic chemical vapor deposition of oxide dielectrics on N-polar III-nitride semiconductors with high interface quality and tunable fixed interface charge
    Patent number: 9281183
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 8, 2016
    Assignee: The Regents of the University of California
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan
  • METALORGANIC CHEMICAL VAPOR DEPOSITION OF OXIDE DIELECTRICS ON N-POLAR III-NITRIDE SEMICONDUCTORS WITH HIGH INTERFACE QUALITY AND TUNABLE FIXED INTERFACE CHARGE
    Publication number: 20150200286
    Abstract: A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 16, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xiang Liu, Umesh K. Mishra, Stacia Keller, Jeonghee Kim, Matthew Laurent, Jing Lu, Ramya Yeluri, Silvia H. Chan