Abstract: Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating.

Abstract: Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating.