Abstract: A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.

Abstract: A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Abstract: In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

Abstract: A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a key-generating instruction. The execution unit includes a key generation circuit that, responsive to a key-generating instruction, iteratively applies a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from the architected register file and stores, within the architected register file, a decryption key obtained from at least one iteration of the cryptographic function.

Abstract: Generation of test data for verifying a modular correction of a modular multiplication performed by a multiplier unit for very wide operands includes performing, by a multiplier unit using a computer, a modular multiplication by correcting a binary multiplication of two operands by a coarse-grained and a fine-grained correction. The computer selects adjacent intervals of the intermediate result, defines a sub-interval closely around a boundary between the adjacent intervals, and selects a value in the sub-interval. Moreover, the computer uses a first factorization algorithm for the value V for determining operands A?, B?, where the modular multiplication result of the operands corrected by the coarse-grained correction is in the sub-interval. The computer repeatedly determines A? plus varying ?-values as A? values, and determines B? values, so that the modular multiplication corrected by the coarse-grained correction is in the sub-interval.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes scaling the input value to provide a scaled result and converting the scaled result from the one format to provide a converted result in the other format. The scaling and converting are to be performed as part of executing the instruction. The converted result in the other format is provided to be used in processing within the computing environment.

Abstract: A hardware device is provided to perform a plurality of operations to convert an input value directly from one format to another format. The hardware device is to perform the plurality of operations based on execution of an instruction. The plurality of operations includes converting one part of the input value to provide a converted value, performing one or more arithmetic operations on another part of the input value to provide an intermediate value, and using the converted value and the intermediate value to provide a converted result in the other format. The converting, the performing and the using are performed as part of executing the instruction. The converted result in the other format is to be used in processing within the computing environment.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Abstract: In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.

Abstract: An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

Abstract: An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Abstract: An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.

Abstract: Methods and systems for division operation are described. A processor can initialize an estimated quotient between the dividend and the divisor separately from a floating-point unit (FPU) pipeline. The processor can implement the FPU pipeline to execute a refinement process that can include at least a first iteration of operations and a second iteration of operations. The refinement process can include, in the first iteration of operations, generating a first unnormalized floating-point value using the initialized estimated quotient. The refinement process can include, in the second iteration of operations, generating a second unnormalized floating-point value using the first unnormalized floating-point value. The processor can determine a final quotient based on the second unnormalized floating-point value.

Abstract: An example computer-implemented method includes receiving a first value, a second value, a third value, and a fourth value, wherein the first value, the second value, the third value, and the fourth value are 16-bit or smaller precision floating-point numbers. The method further includes multiplying the first value and the second value to generate a first product, wherein the first product is a 32-bit floating-point number. The method further includes multiplying the third value and the fourth value to generate a second product, wherein the second product is a 32-bit floating-point number. The method further includes summing the first product and the second product to generate a summed value, wherein the summed value is a 32-bit floating-point number. The method further includes adding the summed value to an addend value to generate a result value, wherein the addend value and the result value are 32-bit floating-point numbers.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.