Patents by Inventor Silvia Melitta Mueller
Silvia Melitta Mueller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8219605Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.Type: GrantFiled: May 28, 2010Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Michael F. Cowlishaw, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh
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Patent number: 8166085Abstract: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.Type: GrantFiled: April 18, 2008Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Christian Jacobi, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 8131795Abstract: A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.Type: GrantFiled: November 25, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20110320512Abstract: A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N?1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Adam B. Collura, Michael Kroener, Silvia Melitta Mueller
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Publication number: 20110296229Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.Type: ApplicationFiled: May 28, 2010Publication date: December 1, 2011Applicant: International Business Machines CorporationInventors: MICHAEL F. COWLISHAW, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh
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Publication number: 20100174764Abstract: A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.Type: ApplicationFiled: January 8, 2009Publication date: July 8, 2010Applicant: International Business Machines CorporationInventors: Maarten Boersma, Markus Kaltenbach, Michael Klein, Silvia Melitta Mueller, Jochen Preiss
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Publication number: 20100146023Abstract: A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result.Type: ApplicationFiled: December 10, 2008Publication date: June 10, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten Boersma, Silvia Melitta Mueller, Jochen Preiss, Holger Wetter
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Publication number: 20100100578Abstract: A distributed residue checking apparatus for a floating point unit having a plurality of functional elements performing floating-point operations on a plurality of operands. The distributed residue checking apparatus includes a plurality of residue generators which generate residue values for the operands and the functional elements, and a plurality of residue checking units distributed throughout the floating point unit. Each residue checking unit receives a first residue value and a second residue value from respective residue generators and compares the first residue value to the second residue value to determine whether an error has occurred in a floating-point operation performed by a respective functional element.Type: ApplicationFiled: October 17, 2008Publication date: April 22, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Son Trong Dao, Juergen Georg Haess, Michael Klaus Kroener, Silvia Melitta Mueller, Jochen Preiss
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Publication number: 20090077155Abstract: A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.Type: ApplicationFiled: November 25, 2008Publication date: March 19, 2009Inventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7490119Abstract: An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.Type: GrantFiled: December 11, 2003Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20090024684Abstract: A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.Type: ApplicationFiled: September 26, 2008Publication date: January 22, 2009Applicant: IBM CORPORATIONInventors: Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7469265Abstract: In a first aspect, a method is provided for determining in which of n intervals a sum of two or more numbers resides. The method includes determining the two or more numbers, and providing fewer than n compress circuits each adapted to (1) input the two or more numbers; (2) input range information regarding ranges used to define the n intervals; and (3) compress the two or more numbers and the range information into two or more outputs. The method further includes employing the fewer than n compress circuits to determine in which of the n intervals the sum of the two or more numbers resides. Numerous other aspects are provided.Type: GrantFiled: October 16, 2003Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 7461117Abstract: The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of tType: GrantFiled: February 11, 2005Date of Patent: December 2, 2008Assignee: International Business Machines CorporationInventors: Son Dao Trong, Juergen Haess, Christian Jacobi, Klaus Michael Kroener, Silvia Melitta Mueller, Jochen Preiss
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Patent number: 7447725Abstract: An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.Type: GrantFiled: November 5, 2004Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20080263336Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: ApplicationFiled: June 24, 2008Publication date: October 23, 2008Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
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Publication number: 20080195684Abstract: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.Type: ApplicationFiled: April 18, 2008Publication date: August 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sang Hoo Dhong, Christian Jacobi, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 7406589Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: GrantFiled: May 12, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7392270Abstract: The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.Type: GrantFiled: July 29, 2004Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Christian Jacobi, Silvia Melitta Mueller, Hiroo Nishikawa, Hwa-Joon Oh
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Patent number: 7290023Abstract: A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.Type: GrantFiled: November 20, 2003Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Silvia Melitta Mueller, Hwa-Joon Oh, Kevin D. Tran
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Patent number: 7245159Abstract: A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.Type: GrantFiled: July 15, 2004Date of Patent: July 17, 2007Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Christian Jacobi, Hwa-Joon Oh, Silvia Melitta Mueller