Abstract: A computer system and method for programming it for storage of individual medical histories on a storage device, preferably about the size of a credit card, for adding new medical data about the individual to the device and for communicating with other computers to retrieve large data records about the individual; and for enabling a second computer to collate and sort data relating to selected medical fields from the data of such individual and from the data about other individuals transferred to the second computer.

Abstract: A computer system and method for programming it for storage of individual medical histories on a storage device, preferably about the size of a credit card, for adding new medical data about the individual to the device and for communicating with other computers to retrieve large data records about the individual; and for enabling a second computer to collate and sort data relating to selected medical fields from the data of such individual and from the data about other individuals transferred to the second computer.

Abstract: This invention is a novel high-speed neural network based processor for solving the "traveling salesman" and other global optimization problems. It comprises a novel hybrid architecture employing a binary synaptic array whose embodiment incorporates the fixed rules of the problem, such as the number of cities to be visited. The array is prompted by analog voltages representing variables such as distances. The processor incorporates two interconnected feedback networks, each of which solves part of the problem independently and simultaneously, yet which exchange information dynamically.

Abstract: A neural network processor for solving first-order competitive assignment problems consists of a matrix of N.times.M processing units, each of which corresponds to the pairing of a first number of elements of {R.sub.i } with a second number of elements {C.sub.j }, wherein limits of the first number are programmed in row control superneurons, and limits of the second number are programmed in column superneurons as MIN and MAX values. The cost (weight) W.sub.ij of the pairings is programmed separately into each PU. For each row and column of PUs, a dedicated constraint superneuron insures that the number of active neurons within the associated row or column fall within a specified range. Annealing is provided by gradually increasing the PU gain for each row and column or increasing positive feedback to each PU, the latter being effective to increase hysteresis of each PU or by combining both of these techniques.

Abstract: This is a fully parallel analog backpropagation learning processor which comprises a plurality of programmable resistive memory elements serving as synapse connections whose values can be weighted during learning with buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in a plurality of neuron layers in accordance with delta-backpropagation algorithms modified so as to control weight changes due to circuit drift.

Abstract: A method and associated apparatus for finding the lowest cost path of several variable paths comprising a plurality of linked cost-incurring areas existing between an origin point and a destination point. The method comprises the steps of, connecting a plurality of nodes together in the manner of the cost-incurring areas; programming each node to have a cost associated therewith corresponding to one of the cost-incurring areas; injecting a signal into one of the nodes representing the origin point; propagating the signal through the plurality of nodes from inputs to outputs thereof; reducing the signal in magnitude at each node as a function of the respective cost of the node; and, starting at one of the nodes representing the destination point and following a path having the least reduction in magnitude of the signal from node to node back to the one of the nodes representing the origin point whereby the lowest cost path from the origin point to the destination point is found.

Abstract: This is a recurrent or feedforward analog neural network processor having a multi-level neuron array and a synaptic matrix for storing weighted analog values of synaptic connection strengths which is characterized by temporarily changing one connection strength at a time to determine its effect on system output relative to the desired target. That connection strength is then adjusted based on the effect, whereby the processor is taught the correct response to training examples connection by connection.