Abstract: A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.

Abstract: Embodiments of the invention provide a method that includes partitioning a series of instructions of a trace into a plurality of dependency sets before executing the trace; and marking a first group of the dependency sets as critical and a second group of the dependency sets as non-critical Embodiments of the invention also provide a method that may identify a dependency set in the second group, which delays the execution of at least one dependency set in the first group, as a delaying dependency set; counting the number of delays caused by the delaying dependency set; and re-marking the delaying dependency set as critical when a predefined delaying event threshold is reached.

Abstract: Methods and systems provide for the fusing of multiple operations into a single micro-operation (uop). A method of decoding a macro-instruction provides for transferring data relating to a first operation from the macro-instruction to a uop. The uop is to be executed by an execution system of a processor. The method further provides for transferring data relating to a second operation from the macro-instruction to the uop.

Abstract: Methods and apparatuses for distributing architectural state information in a processor across multiple pipeline stages are described. An architectural value of a register is represented by a historical value added to an update value which is maintained in a non-final pipeline stage. When an instruction requires the architectural value, a calculation is made and that value is inserted into the pipeline for processing. Recovery of both pre- and post-execution architectural state information is made possible by storing both the update value and the operation to take place on that value for each decoded instruction.

Abstract: A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.

Abstract: Methods and systems provide for the fusing of multiple operations into a single micro-operation (uop). A method of decoding a macro-instruction provides for transferring data relating to a first operation from the macro-instruction to a uop. The uop is to be executed by an execution system of a processor. The method further provides for transferring data relating to a second operation from the macro-instruction to the uop.

Abstract: A return stack buffer mechanism that uses two separate return stack buffers is disclosed. The first return stack buffer is the Speculative Return Stack Buffer. The Speculative Return Stack Buffer is updated using speculatively fetched instructions. Thus, the Speculative Return Stack Buffer may become corrupted when incorrect instructions are fetched. The second return stack buffer is the Actual Return Stack Buffer. The Actual Return Stack Buffer is updated using information from fully executed branch instructions. When a branch misprediction causes a pipeline flush, the contents of the Actual Return Stack Buffer is copied into the Speculative Return Stack Buffer to correct any corrupted information.

Abstract: Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes.

Abstract: Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes.

Abstract: A Branch Target Buffer Circuit in a computer processor that predicts branch instructions within a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache with multiple BTB banks that store branch information about previously executed branch instructions. The branch information stored in each bank of the Branch Target Buffer Cache is addressed by the last byte of each branch instruction When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache banks to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an instruction Fetch Unit about the upcoming branch instruction.

Abstract: To improve computer performance, a second processor can be added to a computer system. However, when a second processor is added to a computer system, a dual processing protocol is required to ensure that the two processors share the computer resources. A robust dual processing protocol is introduced that allows two processors to share a single processor bus in an efficient manner. The dual processing protocol allows pipelined bus transfers wherein partial control of the bus is transferred. Furthermore, the dual processing protocol ensures cache coherency by having any modified cache line written back to main memory when a memory location represent by a modified internal cache line is accessed. The dual processing Protocol is designed to support a well defined fair and robust arbitration DP protocol between two processors that is independent of the core frequency and the bus fraction ratio.

Abstract: An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

Abstract: An improved cache memory for use with a microprocessor. A line buffer which stores a tag and offset field and the corresponding line of data is employed. Valid bits are associated with different potions of the data stored in the line buffer. Thus during a line fill, by way of example, an instruction may be read from the line buffer before the entire line is filled from main memory.

Abstract: An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.