Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

Abstract: A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Abstract: A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.

Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

Abstract: An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).